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Details, datasheet, quote on part number:GS8321V36E-250I
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Datasheet text preview:
GS8321V18/32/36E-250/225/200/166/150/133 165-Bump FP-BGA Commercial Temp Industrial Temp Features
· IEEE 1149.1 JTAG-compatible Boundary Scan · 1.8 V +10%/10% core power supply · 1.8 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 165-bump FP-BGA package -250 -225 -200 -166 -150 -133 Unit 2.3 2.5 2.7 2.9 3.3 3.5 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 285 350 6.5 6.5 205 235 265 320 7.0 7.0 195 225 245 295 7.5 7.5 185 210 220 260 8.0 8.0 175 200 210 240 8.5 8.5 165 190 185 215 8.5 8.5 155 175 mA mA ns ns mA mA
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
Flow Through/Pipeline Reads
250 MHz133 MHz 1.8 V VDD 1.8 V I/O
The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edgetriggered Data Output Register.
SCD Pipelined Reads
The GS8321V18/32/36E is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Pipeline 3-1-1-1 Flow Through 2-1-1-1
tK Q tCycle Curr (x18) Curr (x36) tK Q tCycle Curr (x18) Curr (x36)
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS8321V18/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS8321V18/32/36E operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Rev: 1.01 6/2003
1/31
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321V18/32/36E-250/225/200/166/150/133 165 Bump BGA--x18 Commom I/O--Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQPB NC L BO 2 A A NC DQB DQB DQB DQB MCL NC NC NC NC NC NC A 3 E1 E2 VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A A 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S A A1 A0 7 BW GW VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC TDO TCK 8 ADSC G VS S VD D VD D VD D VD D VD D VD D VD D VD D VD D VS S A A 9 ADV ADSP VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A A 10 A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A A B C D E F G H J K L M N P R
11 x 15 Bump BGA--15 mm x 17 mm Body--1.0 mm Bump Pitch
Rev: 1.01 6/2003
2/31
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321V18/32/36E-250/225/200/166/150/133 165 Bump BGA--x32 Common I/O--Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC NC DQC DQC DQC DQC FT DQD DQD DQD DQD NC NC L BO 2 A A NC DQC DQC DQC DQC MCL DQD DQD DQD DQD NC NC A 3 E1 E2 VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S A A1 A0 7 BW GW VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC TDO TCK 8 ADSC G VS S VD D VD D VD D VD D VD D VD D VD D VD D VD D VS S A A 9 ADV ADSP VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A A 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC NC DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC A A A B C D E F G H J K L M N P R
11 x 15 Bump BGA--15 mm x 17 mm Body--1.0 mm Bump Pitch
Rev: 1.01 6/2003
3/31
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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