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Details, datasheet, quote on part number:GS8321Z32E-166
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Datasheet text preview:
GS8321Z18/32/36E-250/225/200/166/150/133 165-Bump FP-BGA Commercial Temp Industrial Temp Features
· User-configurable Pipeline and Flow Through mode · NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization · Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · IEEE 1149.1 JTAG-compatible Boundary Scan · 2.5 V or 3.3 V +10%/10% core power supply · LBO pin for Linear or Interleave Burst mode · Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · ZZ pin for automatic power-down · JEDEC-standard 165-bump FP-BGA package tK Q tCycle Curr (x18) Curr (x32/x36) tK Q Flow tCycle Through Curr (x18) 2-1-1-1 Curr (x32/x36) Pipeline 3-1-1-1 -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.5 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.6 7.5 ns 285 350 6.5 6.5 205 235 265 320 7.0 7.0 195 225 245 295 7.5 7.5 185 210 220 210 185 mA 260 240 215 mA 8.0 8.5 8.5 ns 8.0 8.5 8.5 ns 175 165 155 mA 200 190 175 mA
36Mb Pipelined and Flow Through Synchronous NBT SRAM
250 MHz133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8321Z18/32/36E is implemented with GSI's high performance CMOS technology and is available in JEDECstandard 165-bump FP-BGA package.
Functional Description
The GS8321Z18/32/36E is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8321Z18/32/36E may be configured by the user to Rev: 1.00b 1/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 2003, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8321Z18/32/36E-250/225/200/166/150/133 165 Bump BGA--x18 Commom I/O--Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQPB NC L BO 2 A6 A7 NC DQB DQB DQB DQB MCH NC NC NC NC NC NC A19 3 E1 E2 VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A5 A3 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A4 A2 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC A1 A0 7 CKE W VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC TDO TCK 8 ADV G VS S VD D VD D VD D VD D VD D VD D VD D VD D VD D VS S A11 A 10 9 A17 A18 VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A12 A13 10 A8 A9 NC NC NC NC NC NC DQA DQA DQA DQA NC A14 A15 11 A20 NC DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC NC A16 A B C D E F G H J K L M N P R
11 x 15 Bump BGA--15 mm x 17 mm Body--1.0 mm Bump Pitch
Rev: 1.00b 1/2003
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© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321Z18/32/36E-250/225/200/166/150/133 165 Bump BGA--x32 Common I/O--Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC NC DQC DQC DQC DQC FT DQD DQD DQD DQD NC NC L BO 2 A6 A7 NC DQC DQC DQC DQC MCH DQD DQD DQD DQD NC NC A19 3 E1 E2 VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A5 A3 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A4 A2 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC A1 A0 7 CKE W VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC TDO TCK 8 ADV G VS S VD D VD D VD D VD D VD D VD D VD D VD D VD D VS S A11 A 10 9 A17 A18 VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A12 A13 10 A8 A9 NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A14 A15 11 NC NC NC DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC NC A16 A B C D E F G H J K L M N P R
11 x 15 Bump BGA--15 mm x 17 mm Body--1.0 mm Bump Pitch
Rev: 1.00b 1/2003
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© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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