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Details, datasheet, quote on part number:GS8322V72C-166I
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Datasheet text preview:
Product Preview GS8322V18(B/E)/GS8322V 36(B/E)/GS8322V72(C) 119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features
2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
Flow Through/Pipeline Reads
250 MHz133MHz 1.8 V VDD 1.8 V I/O
· FT pin for user-configurable flow through or pipeline operation · Single/Dual Cycle Deselect selectable · IEEE 1149.1 JTAG-compatible Boundary Scan · ZQ mode pin for user-selectable high/low output drive · 1.8 V +10%/10% core power supply · 1.8 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to SCD x18/x36 Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 119-, 165-, and 209-bump BGA package
The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
Pipeline 3-1-1-1
Flow Through 2-1-1-1
tKQ(x18/x36) tKQ(x72) tCycle Curr (x18) Curr (x36) Curr (x72) tK Q tCycle Curr (x18) Curr (x36) Curr (x72)
-250 -225 2.3 2.5 2.6 2.7 4.0 4.4 285 350 440 6.5 6.5 205 235 315
-200 2.7 2.8 5.0
-166 2.9 2.9 6.0
-150 3.3 3.3 6.7
-133 Unit 3.5 ns 3.5 ns 7.5 ns
The GS8322V18/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
265 245 220 210 185 m A 320 295 260 240 215 m A 410 370 320 300 265 m A 7.0 7.0 7.5 7.5 8.0 8.0 8.5 8.5 8.5 8.5 ns ns
Byte Write and Global Write
195 185 175 165 155 m A 225 210 200 190 175 m A 295 265 255 240 230 m A
FLXDriveTM
Functional Description
Applications
The GS8322V18/36/72 is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. The GS8322V18/36/72 operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.
Core and Interface Voltages
Controls
Rev: 1.01 6/2003
1/41
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Product Preview GS8322V18(B/E)/GS8322V 36(B/E)/GS8322V72(C) GS832272C Pad Out 209-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U V W DQG DQG DQG DQG D Q PG D QC D QC D QC D QC NC D QH D QH D QH D QH D Q PD D QD D QD D QD D QD 2 D QG D QG D QG D QG D Q PC D QC D QC D QC D QC NC D QH D QH D QH D QH D Q PH D QD D QD D QD D QD 3 A BC BH VSS VD D Q VSS VD D Q VSS VD D Q CK VD D Q VSS VD D Q VSS VD D Q VSS NC A TMS 4 E2 BG BD NC VD D Q VSS VD D Q VSS VD D Q NC VD D Q VSS VD D Q VSS VD D Q NC A A TDI 5 AD SP NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 6 ADSC BW E1 G VD D ZQ MCH MCL MCL MCL FT MCL SCD ZZ VD D LBO A A1 A0 7 ADV A NC GW VD D VS S VD D VS S VD D VS S VD D VS S VD D VS S VD D NC A A A 8 E3 BB BE NC VD D Q VS S VD D Q VS S VD D Q NC VD D Q VS S VD D Q VS S VD D Q NC A A TDO 9 A BF BA VS S VD D Q VS S VD D Q VS S VD D Q NC VD D Q VS S VD D Q VS S VD D Q VSS A A TCK 10 D QB D QB D QB D QB DQPF D QF D QF D QF D QF NC D QA D QA D QA D QA DQPA D QE DQE DQE DQE 11 D QB D QB D QB D QB DQPB D QF D QF D QF D QF NC D QA D QA D QA D QA DQPE D QE D QE D QE D QE A B C D E F G H J K L M N P R T U V W
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.01 6/2003
2/41
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8322V18(B/E)/GS8322V 36(B/E)/GS8322V72(C)
GS8322V72 209-Bump BGA Pin Description
Symbol
A0, A1 An D QA D QB D QC D QD D QE DQF DQG D QH BA, BB BC,BD BE, BF, BG,BH NC CK GW E1 E3 E2 G ADV ADSP, ADSC ZZ FT LBO SCD MCH
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs. Address Inputs
I/O
Data Input and Output pins
I I I -- I I I I I I I I I I I I I
Byte Write Enable for DQA, DQB I/Os; active low Byte Write Enable for DQC, DQD I/Os; active low Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control Must Connect High
Rev: 1.01 6/2003
3/41
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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