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Details, datasheet, quote on part number:GS8322Z18B-225I
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Datasheet text preview:
Product Preview GS8322Z18(B/E)/GS8322Z3 6 ( B / E ) / G S 8 3 2 2 Z 7 2 ( C ) 119, 165 & 209 BGA Commercial Temp Industrial Temp Features
· NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · User-configurable Pipeline and Flow Through mode · ZQ mode pin for user-selectable high/low output drive · IEEE 1149.1 JTAG-compatible Boundary Scan · LBO pin for Linear or Interleave Burst mode · Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · ZZ Pin for automatic power-down · JEDEC-standard 119-, 165- or 209-Bump BGA package -250 -225 2.5 2.7 3.0 3.0 4.0 4.4 285 350 440 6.5 6.5 205 235 315 -200 3.0 3.0 5.0 -166 3.5 3.5 6.0 -150 3.8 3.8 6.7 -133 Unit 4.0 ns 4.0 ns 7.5 ns
36Mb Pipelined and Flow Through Synchronous NBT SRAM
and simplifies input signal timing.
250 MHz133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
The GS8322Z18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8322Z18/36/72 is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 119-bump, 165-bump or 209-bump BGA package.
Pipeline 3-1-1-1
Flow Through 2-1-1-1
tKQ(x18/x36) tKQ(x72) tCycle Curr (x18) Curr (x36) Curr (x72) tK Q tCycle Curr (x18) Curr (x36) Curr (x72)
265 245 220 210 185 m A 320 295 260 240 215 m A 410 370 320 300 265 m A 7.0 7.0 7.5 7.5 8.0 8.0 8.5 8.5 8.5 8.5 ns ns
195 185 175 165 155 m A 225 210 200 190 175 m A 295 265 255 240 230 m A
Functional Description
The GS8322Z18/36/72 is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs Rev: 1.03c 2/2003 1/38 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Product Preview GS8322Z18(B/E)/GS8322Z3 6 ( B / E ) / G S 8 3 2 2 Z 7 2 ( C ) GS8322Z72C Pad Out 209-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U V W DQG DQG DQG DQG D Q PG D QC D QC D QC D QC NC D QH D QH D QH D QH D Q PD D QD D QD D QD D QD 2 D QG D QG D QG D QG D Q PC D QC D QC D QC D QC NC D QH D QH D QH D QH D Q PH D QD D QD D QD D QD 3 A BC BH VSS VD D Q VSS VD D Q VSS VD D Q CK VD D Q VSS VD D Q VSS VD D Q VSS NC A TMS 4 E2 BG BD NC VD D Q VSS VD D Q VSS VD D Q NC VD D Q VSS VD D Q VSS VD D Q NC A A TDI 5 A NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC A A 6 ADV W E1 G VD D ZQ MCH MCL MCH CKE FT MCL MCH ZZ VD D LBO A A1 A0 7 A A NC NC VD D VS S VD D VS S VD D VS S VD D VS S VD D VS S VD D NC A A A 8 E3 BB BE NC VD D Q VS S VD D Q VS S VD D Q NC VD D Q VS S VD D Q VS S VD D Q NC A A TDO 9 A BF BA VSS VD D Q VS S VD D Q VS S VD D Q NC VD D Q VS S VD D Q VS S VD D Q VSS NC A TCK 10 D QB D QB D QB D QB DQPF D QF D QF D QF D QF NC D QA D QA D QA D QA DQPA D QE DQE DQE DQE 11 D QB D QB D QB D QB DQPB D QF D QF D QF D QF NC D QA D QA D QA D QA DQPE D QE D QE D QE D QE A B C D E F G H J K L M N P R T U V W
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.03c 2/2003
2/38
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8322Z18(B/E)/GS8322Z3 6 ( B / E ) / G S 8 3 2 2 Z 7 2 ( C ) GS8322Z72 209-Bump BGA Pin Description
Symbol
A0, A1 An D QA D QB D QC D QD D QE DQF DQG D QH BA, BB BC,BD BE, BF, BG,BH NC CK E1 E3 E2 G ADV ZZ FT LBO MCH MCH MCL W ZQ CKE I I I
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs
I/O
Data Input and Output pins
I I I -- I I I I I I I I I I I
Byte Write Enable for DQA, DQB I/Os; active low Byte Write Enable for DQC, DQD I/Os; active low Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Must Connect High Must Connect High Must Connect Low Write Enable; active low FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive] Clock Enable; active low
Rev: 1.03c 2/2003
3/38
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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