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Part: GS832472C-225I
Category:
Memory
-> SRAM
-> Sync. SRAM
-> Sychronous Burst
Description: 225MHz 6.5ns 1M X 36 36Mb Scd/dcd Pipeline/flow Through SRAM
Company: GSI Technology
Datasheet: Download GS832472C-225I datasheet File size : 685 kB
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Datasheet text preview:
Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) 119- and 209-Pin BGA Commercial Temp Industrial Temp Features
· FT pin for user-configurable flow through or pipeline operation · Single/Dual Cycle Deselect selectable (x36 and x72) · Dual Cycle Deselect only (x18) · IEEE 1149.1 JTAG-compatible Boundary Scan · ZQ mode pin for user-selectable high/low output drive · 2.5 V or 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to SCD x36/x72 Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 119- and 209-bump BGA package
2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
250 MHz133MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS832436(B/C) and the GS832472(C) are SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAMs. The GS832418(B/C) is a DCD-only SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure the x36 or x72 versions of this SRAM for either mode of operation using the SCD mode input.
Pipeline 3-1-1-1 3.3 V
2.5 V Flow Through 2-1-1-1 3.3 V
tK Q tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) tK Q tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72)
-250 -225 -200 -166 -150 -133 Unit 2.3 2.5 3.0 3.5 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.6 7.5 ns 365 560 660 360 550 640 6.0 7.0 235 300 350 235 300 340 335 510 600 330 500 590 6.5 7.5 230 300 350 230 300 340 305 460 540 305 460 530 7.5 8.5 210 270 300 210 270 300 265 400 460 260 390 450 8.5 10 200 270 300 200 270 300 245 370 430 240 360 420 10 10 195 270 300 195 270 300 215 330 380 215 330 370 11 15 150 200 220 145 190 220 mA mA mA mA mA mA ns ns mA mA mA mA mA mA
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
2.5 V
FLXDriveTM
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Functional Description
Applications
The GS832418/36/72 is a 37,748,736-bit high performance 2-die synchronous SRAM module with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832418/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated
Rev: 1.00 10/2001
1/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832472B Pad Out 209-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U V W DQG5 DQG6 DQG7 DQG8 DQPG 9 DQC4 DQC3 DQC2 DQC1 NC DQH1 DQH2 DQH3 DQH4 DQPD 9 DQD8 DQD7 DQD6 DQD5 2 DQG1 DQG2 DQG3 DQG4 DQPC 9 DQC8 DQC7 DQC6 DQC5 NC DQH5 DQH6 DQH7 DQH8 DQPH 9 DQD4 DQD3 DQD2 DQD1 3 A15 BC BH VSS V DDQ VSS V DDQ VSS V DDQ CK V DDQ VSS V DDQ VSS V DDQ VSS NC A9 TMS 4 E2 BG BD NC V DDQ VSS V DDQ VSS V DDQ NC V DDQ VSS V DDQ VSS V DDQ NC A14 A8 TDI 5 ADSP NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A13 A7 A3 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT MCL SCD ZZ VDD LBO A12 A1 A0 7 ADV A16 NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A11 A6 A2 8 E3 BB BE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A10 A5 TDO 9 A17 BF BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A18 A4 TCK 10 DQB1 DQB2 DQB3 DQB4 DQPF 9 DQF8 DQF7 DQF6 DQF5 NC DQA5 DQA6 DQA7 DQA8 DQPA9 DQE4 DQE3 DQE2 DQE1 11 DQB5 DQB6 DQB7 DQB8 DQPB9 DQF4 DQF3 DQF2 DQF1 NC DQA1 DQA2 DQA3 DQA4 DQPE9 DQE8 DQE7 DQE6 DQE5 A B C D E F G H J K L M N P R T U V W
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.00 10/2001
2/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832436C Pad Out 209-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC DQC4 DQC3 DQC2 DQC1 NC NC NC NC NC DQPD 9 DQD8 DQD7 DQD6 DQD5 2 NC NC NC NC DQPC 9 DQC8 DQC7 DQC6 DQC5 NC NC NC NC NC NC DQD4 DQD3 DQD2 DQD1 3 A15 BC NC VSS V DDQ VSS V DDQ VSS V DDQ CK V DDQ VSS V DDQ VSS V DDQ VSS NC A9 TMS 4 E2 NC BD NC V DDQ VSS V DDQ VSS V DDQ NC V DDQ VSS V DDQ VSS V DDQ NC A14 A8 TDI 5 ADSP A19 NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A13 A7 A3 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT MCL SCD ZZ VDD LBO A12 A1 A0 7 ADV A16 NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A11 A6 A2 8 E3 BB NC NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A10 A5 TDO 9 A17 NC BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A18 A4 TCK 10 DQB1 DQB2 DQB3 DQB4 NC NC NC NC NC NC DQA5 DQA6 DQA7 DQA8 DQPA9 NC NC NC NC 11 DQB5 DQB6 DQB7 DQB8 DQPB9 NC NC NC NC NC DQA1 DQA2 DQA3 DQA4 NC NC NC NC NC A B C D E F G H J K L M N P R T U V W
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.00 10/2001
3/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Others parts begin by gs
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