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Details, datasheet, quote on part number:GS840H18B-166I
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Datasheet text preview:
GS840H18/32/36T/B-180/166/150/100 TQFP, BGA Commercial Temp Industrial Temp Features
· FT pin for user configurable flow through or pipelined operation. · Single Cycle Deselect (SCD) Operation. · High Output Drive current. · 3.3V +10%/-5% Core power supply · 2.5V or 3.3V I/O supply. · LBO pin for linear or interleaved burst mode. · Internal input resistors on mode pins allow floating mode pins. · Default to Interleaved Pipelined Mode. · Byte write (BW) and/or global write (GW) operation. · Common data inputs and data outputs. · Clock Control, registered, address, data, and control. · Internal Self-Timed Write cycle. · Automatic power-down for portable applications. · JEDEC standard 100-lead TQFP or 119 Bump BGA package. -180 5.5ns 3.2ns 330mA 8ns 10ns 190mA -166 6.0ns 3.5ns 310mA 8.5ns 10ns 190mA -150 6.6ns 3.8ns 275mA 10ns 10ns 190mA -100 10ns 4.5ns 190mA 12ns 15ns 140mA
256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
Flow Through / Pipeline Reads
180Mhz - 100Mhz 3.3V VDD 3.3V & 2.5V I/O
with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA, ). Holding the FT mode pin/bump low places the RAM in Flow through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined Mode, activating the rising edge triggered Data Output Register.
SCD Pipelined Reads
The GS840H18/32/36 is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available.SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Pipeline 3-1-1-1 Flow Through 2-1-1-1
tCycle tK Q ID D tK Q tCycle ID D
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS840H18/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU's, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS840H18/32/36 is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA package.
Core and Interface Voltages
The GS840H18/32/36 operates on a 3.3V power supply and all inputs/outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit.
Controls
Addresses, data I/O's, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive edge triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order Rev: 2.04 6/2000 1/31 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36T/B-180/166/150/100
GS840H18 100 Pin TQFP Pinout
NC NC NC VDDQ VSS NC NC DQB1 DQB2 V SS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 V DDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G A DS C A DS P A DV A8 A9
A 17 NC NC VDDQ V SS NC DQA 9 DQA 8 DQA 7 V SS V DDQ DQA 6 DQA 5 V SS NC V DD ZZ DQA 4 DQA 3 V DDQ V SS DQA 2 DQA 1 NC NC V SS V DDQ NC NC NC
Rev: 2.04 6/2000
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A3 A2 A1 A0 NC NC V SS VDD NC NC A10 A11 A12 A13 A14 A15 A16 2/31 © 1999, Giga Semiconductor, Inc.
GS840H18/32/36T/B-180/166/150/100
GS840H32 100 Pin TQFP Pinout
NC D Q C8 D Q C7 VDDQ VSS D Q C6 D Q C5 DQC4 D Q C3 VSS VDDQ DQC2 D Q C1 FT VDD NC VSS DQD1 D Q D2 V DDQ VSS DQD3 D Q D4 D Q D5 D Q D6 VSS VDDQ D Q D7 D Q D8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G A DS C A DS P A DV A8 A9
NC DQB 8 DQB 7 VDDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 NC
Rev: 2.04 6/2000
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A3 A2 A1 A0 NC NC V SS VDD NC NC A10 A11 A12 A13 A14 A15 A16 3/31 © 1999, Giga Semiconductor, Inc.
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