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Details, datasheet, quote on part number:GS841Z36AT-166I
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Datasheet text preview:
Preliminary GS841Z18/36AT-180/166/150/100 100-Pin TQFP Commercial Temp Industrial Temp Features
· 256K x 18 and 128K x 36 configurations · User-configurable Pipelined and Flow Through mode · NBT (No Bus Turn Around) functionality allows zero wait · Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · IEEE 1149.1 JTAG-compatible Boundary Scan · 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleave Burst mode · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · Clock Control, registered, address, data, and control · ZZ Pin for automatic power-down · JEDEC-standard 100-lead TQFP package 180 5.5 ns 3.2 ns 335 mA 8 ns 9.1 ns 210 mA 166 6.0 ns 3.5 ns 310 mA 8.5 ns 10 ns 190 mA 150 6.6 ns 3.8 ns 280 mA 10 ns 12 ns 165 mA 100 10 ns 4.5 ns 190 mA 12 ns 15 ns 135 mA
4Mb Pipelined and Flow Through 180 MHz100 MHz 3.3 V VDD Synchronous NBT SRAMs 2.5 V and 3.3 V VDDQ
bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS841Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS841Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECStandard 100-pin TQFP package.
Pipeline 3-1-1-1 Flow Through 2-1-1-1
tC ycl e tKQ ID D tKQ tC ycl e ID D
Functional Description
The GS841Z18/36AT is an 4Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock Address Read/Write
A R
B W QA
C R DB QA 1/30
D W QC DB
E R DD QC
F W QE DD QE
Flow Through Data I/O Pipelined Data I/O
Rev: 1.01c 11/2002
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary GS841Z18/36AT-180/166/150/100 GS841Z18AT Pinout
VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 VD D VSS CK W CKE G ADV NC NC A8 A9
A 17 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
Rev: 1.01c 11/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
LBO A5 A4 A3 A2 A1 A0 TMS TDI VSS VDD TDO TCK A10 A11 A12 A13 A14 A15 A16 2/30 © 2001, Giga Semiconductor, Inc.
Preliminary GS841Z18/36AT-180/166/150/100 GS841Z36AT Pinout
DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 VD D VSS CK W CKE G ADV NC NC A8 A9
DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9
Rev: 1.01c 11/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
LBO A5 A4 A3 A2 A1 A0 TMS TDI VSS VDD TDO TCK A10 A11 A12 A13 A14 A15 A16 3/30 © 2001, Giga Semiconductor, Inc.
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