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Part: GS842Z36AB-180
Category:
Memory
-> SRAM
-> No Bus Turnaround
Description: 180MHz 8ns 256K X 36 4Mb Pipelined And Flow Through Synchronous NBT SRAM
Company: GSI Technology
Datasheet: Download GS842Z36AB-180 datasheet File size : 1615 kB
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Datasheet text preview:
Preliminary GS842Z18/36AB-180/166/150/100 119-Bump BGA Commercial Temp Industrial Temp Features
· 256K x 18 and 128K x 36 configurations · User configurable Pipeline and Flow Through mode · NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization · Fully pin compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · Pin-compatible with 2M, 8M, and 16M devices · 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleave Burst mode · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · Clock Control, registered address, data, and control · ZZ Pin for automatic power-down · JEDEC-standard 119-bump BGA package 180 5.5 ns 3.2 ns 335 mA 8 ns 9.1 ns 210 mA 166 6.0 ns 3.5 ns 310 mA 8.5 ns 10 ns 190 mA 150 6.6 ns 3.8 ns 280 mA 10 ns 12 ns 165 mA 100 10 ns 4.5 ns 190 mA 12 ns 15 ns 135 mA
4Mb Pipelined and Flow Through 180 MHz100 MHz 3.3 V VDD Synchronous NBT SRAMs 2.5 V and 3.3 V VDDQ
Functional Description
The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS842Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS842Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 119-bump BGA package.
Pipeline 3-1-1-1 Flow Through 2-1-1-1
tC ycl e tKQ ID D tKQ tC ycl e ID D
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock Address Read/Write
A R
B W QA
C R DB QA
D W QC DB
E R DD QC
F W QE DD QE
Flow Through Data I/O Pipelined Data I/O
Rev: 1.02 11/2002
1/32
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary GS842Z18/36AB-180/166/150/100 GS842Z18A Pad Out
119 Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U VDDQ NC NC D QB 1 NC VDDQ NC D QB 4 VDDQ NC D QB 6 VDDQ D QB 8 NC NC NC VDDQ 2 A6 E2 A5 NC DQB2 NC DQB3 NC VD D DQB5 NC D QB 7 NC DQB9 A2 A1 0 TMS 3 A7 A4 A3 VS S VS S VS S BB VS S NC VS S NC VS S VS S VS S LBO A11 TDI 4 NC ADV VD D ZQ E1 G NC W VD D CK NC CKE A1 A0 VD D NC TCK 5 A8 A 15 A 14 VSS VS S VS S NC VS S NC VS S BA VS S VS S VS S FT A 12 TDO 6 A9 E3 A 16 D QA 9 NC D QA 7 NC D QA 5 VD D NC D QA 3 NC D QA 2 NC A 13 A 17 NC 7 VD D Q NC NC NC DQA8 VD D Q DQA6 NC VD D Q DQA4 NC VD D Q NC DQA1 NC ZZ VDDQ
Rev: 1.02 11/2002
2/32
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary GS842Z18/36AB-180/166/150/100 GS842Z36A Pad Out
119 Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U VDDQ NC NC D QC 4 D QC 3 VDDQ D QC 2 D QC 1 VDDQ D QD 1 D QD 2 VDDQ D QD 3 D QD 4 NC NC VDDQ 2 A6 E2 A5 D QC 9 D QC 8 D QC 7 D QC 6 D QC 5 VD D D QD 5 D QD 6 D QD 7 D QD 8 D QD 9 A2 NC TMS 3 A7 A4 A3 VS S VS S VS S BC VS S NC VS S BD VS S VS S VS S LBO A1 0 TDI 4 NC ADV VD D ZQ E1 G NC W VD D CK NC CKE A1 A0 VD D A11 TCK 5 A8 A15 A 14 VSS VS S VS S BB VS S NC VS S BA VS S VS S VS S FT A 12 TDO 6 A9 E3 A 16 D QB 9 D QB 8 D QB 7 D QB 6 D QB 5 VD D D QA 5 D QA 6 D QA 7 D QA 8 D QA 9 A 13 NC NC 7 VD D Q NC NC D QB 4 D QB 3 VD D Q D QB 2 D QB 1 VD D Q D QA 1 D QA 2 VD D Q D QA 3 D QA 4 NC ZZ VDDQ
Rev: 1.02 11/2002
3/32
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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