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Details, datasheet, quote on part number:GS880E36T-11I
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Datasheet text preview:
Preliminary GS880E18/32/36T-11/11.5/100/80/66 100-Pin TQFP Commercial Temp Industrial Temp
Features
· FT pin for user-configurable flow through or pipelined operation · Dual Cycle Deselect (DCD) operation · 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Common data inputs and data outputs · Clock Control, registered, address, data, and control · Internal self-timed write cycle · Automatic power-down for portable applications · 100-lead TQFP package - 11 -11.5 - 100 - 80 -66 10 ns 10 ns 12.5 ns 15 ns Pipeline tCycle 10 ns 4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns 3-1-1-1 tK Q 225 mA 225 mA 225 mA 200 mA 185 mA ID D 11 ns 11.5 ns 12 ns 14 ns 18 ns Flow tK Q 15 ns 15 ns 15 ns 20 ns Through tCycle 15 ns 2-1-1-1 IDD 180 mA 180 mA 180 mA 175 mA 165 mA
512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
Flow Through / Pipeline Reads
100 MHz66 MHz 3.3 V VDD 3.3 V and 2.5 V I/O
interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
DCD Pipelined Reads
The GS880E18/32/36T is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs.
Functional Description
Applications
The GS880E18/32/36T is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880E18/32/36T operates on a 3.3 V power supply, and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or Rev: 1.11 11/2000 1/25 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS880E18/32/36T-11/11.5/100/80/66
GS880E18 100-Pin TQFP Pinout
NC NC NC VDDQ VSS NC NC DQB1 DQB2 V SS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 V DDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
A 18 NC NC VDDQ V SS NC DQA 9 DQA 8 DQA 7 V SS V DDQ DQA 6 DQA 5 V SS NC V DD ZZ DQA 4 DQA 3 V DDQ V SS DQA 2 DQA 1 NC NC V SS V DDQ NC NC NC
Rev: 1.11 11/2000
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC V SS VDD NC A17 A10 A11 A12 A13 A14 A15 A16 2/25 © 2000, Giga Semiconductor, Inc.
Preliminary GS880E18/32/36T-11/11.5/100/80/66
GS880E32 100-Pin TQFP Pinout
NC D Q C8 D Q C7 VDDQ V SS D Q C6 D Q C5 DQC4 D Q C3 VSS VDDQ DQC2 D Q C1 FT VDD NC VSS DQD1 D Q D2 VDDQ VSS DQD3 D Q D4 D Q D5 D Q D6 V SS V DDQ D Q D7 D Q D8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9
NC DQB 8 DQB 7 V DDQ V SS DQB 6 DQB 5 DQB 4 DQB 3 V SS V DDQ DQB 2 DQB 1 V SS NC V DD ZZ DQA 1 DQA 2 V DDQ V SS DQA 3 DQA 4 DQA 5 DQA 6 V SS V DDQ DQA 7 DQA 8 NC
Rev: 1.11 11/2000
LBO A5 A4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A3 A2 A1 A0 NC NC VSS V DD NC A17 A10 A11 A12 A13 A14 A15 A16 3/25 © 2000, Giga Semiconductor, Inc.
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