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Part: GS881E18T-66I
Category:
Description: 66MHz 18ns 514K X 18 8Mb SYNC Burst SRAM
Company: GSI Technology
Datasheet: Download GS881E18T-66I datasheet File size : 1698 kB
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Datasheet text preview:
Preliminary GS881E18/36T-11/11.5/100/80/66 100-Pin TQFP Commercial Temp Industrial Temp
1.10 9/2000Features
· FT pin for user-configurable flow through or pipelined operation · Dual Cycle Deselect (DCD) operation · IEEE 1149.1 JTAG-compatible Boundary Scan · On-chip write parity checking; even or odd selectable · 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Common data inputs and data outputs · Clock Control, registered, address, data, and control · Internal self-timed write cycle · Automatic power-down for portable applications · 100-lead TQFP package -11 -11.5 -100 - 80 - 66 10 ns 10 ns 12.5 ns 15 ns Pipeline tCycle 10 ns 4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns 3-1-1-1 tKQ 225 mA 225 mA 225 mA 200 mA 185 mA IDD 11 ns 11.5 ns 12 ns 14 ns 18 ns Flow tKQ 15 ns 15 ns 15 ns 20 ns Through tCycle 15 ns 2-1-1-1 IDD 180 mA 180 mA 180 mA 175 mA 165 mA
512K x 18, 256K x 36 ByteSafeTM 100 MHz66 MHz 3.3 V VDD 8Mb Sync Burst SRAMs 3.3 V and 2.5 V I/O
counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
DCD Pipelined Reads
The GS881E18//36T is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs.
ByteSafeTM Parity Functions
Functional Description
Applications
The GS881E18//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
The GS881E18/36T features ByteSafe data security functions. See detailed discussion following.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18//36T operates on a 3.3 V power supply, and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address Rev: 1.10 9/2000 1/34
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS881E18/36T-11/11.5/100/80/66
GS881E18 100-Pin TQFP Pinout
NC NC NC V DDQ VSS NC NC DQB1 DQB2 VSS V DDQ DQB3 DQB4 FT V DD DP V SS DQB5 DQB6 V DDQ VSS DQB7 DQB8 DQB9 NC V SS V DDQ NC NC NC
100 99 98 9 7 96 95 94 9 3 92 91 90 8 9 88 87 86 8 5 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K X 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 4 9 50
CK GW BW G AD SC AD SP A DV A8 A9
A6 A7 E1 E2 NC NC BB BA A17 V DD VSS
A18 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS QE VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
A1 A0 TMS TD I VSS VDD TD O TCK A10 A11 A12 A13 A14 A15 2/34
LBO A5 A4
Rev: 1.10 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A16 © 2000, Giga Semiconductor, Inc.
A3 A2
Preliminary GS881E18/36T-11/11.5/100/80/66
GS881E36 100-Pin TQFP Pinout
DQ C9 DQ C8 DQ C7 V DDQ VSS DQ C6 DQ C5 DQC4 DQ C3 VSS V DDQ DQC2 DQ C1 FT V DD DP VSS DQD1 DQ D2 VDDQ VSS DQD3 DQ D4 DQ D5 DQ D6 V SS V DDQ DQ D7 DQ D8 DQ D9
100 99 98 9 7 96 95 94 9 3 92 91 90 8 9 88 87 86 8 5 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 4 9 50
CK GW BW G AD SC AD SP A DV A8 A9
A6 A7 E1 E2 BD BC BB BA A17 V DD VSS
DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS QE VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9
A3 A2 A1 A0 TMS T DI VSS VDD T DO TCK A10 A11 A12 A13 A14 A15 3/34
LBO A5 A4
Rev: 1.10 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A16 © 2000, Giga Semiconductor, Inc.
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