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Part: GS881E32BD-166I
Category:
Memory
-> SRAM
-> Sync. SRAM
-> Sychronous Burst
Description:
Company: GSI Technology
Datasheet: Download GS881E32BD-166I datasheet File size : 1698 kB
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Datasheet text preview:
GS881E18B(T/D)/GS881E 32B(D)/GS881E36B(T/D)
100-Pin TQFP & 165-bump BGA Commercial Temp Industrial Temp
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
250 MHz133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
Features
· FT pin for user-configurable flow through or pipeline operation · Dual Cycle Deselect (DCD) operation · IEEE 1149.1 JTAG-compatible Boundary Scan · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 100-lead TQFP and 165-bump BGA packages Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 n s 4.0 4.4 5.0 6.0 6.7 7.5 n s 280 330 275 320 5.5 5.5 175 200 175 200 255 300 250 295 6.0 6.0 165 190 165 190 230 270 230 265 6.5 6.5 160 180 160 180 200 230 195 225 7.0 7.0 150 170 150 170 185 215 180 210 7.5 7.5 145 165 145 165 165 190 165 185 8.5 8.5 135 150 135 150 mA mA mA mA ns ns mA mA mA mA
triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edgetriggered Data Output Register.
DCD Pipelined Reads
The GS881E18B(T/D)/GS881E32B(D)/GS881E36B(T/D) is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Functional Description
Applications
The GS881E18B(T/D)/GS881E32B(D)/GS881E36B(T/D) is a 9,437,184-bit high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18B(T/D)/GS881E32B(D)/GS881E36B(T/D) operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgeRev: 1.00b 12/2002 1/34 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS881E18B(T/D)/GS881E 32B(D)/GS881E36B(T/D)
GS881E18B 100-Pin TQFP Pinout
VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VD D NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 NC NC BB BA A 17 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
A 18 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
Rev: 1.00b 12/2002
LBO A5 A4 A3 A2
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A1 A0 TMS TDI VSS V DD TDO TCK A10 A11 A12 A13 A14 A15 A16 2/34 © 2001, Giga Semiconductor, Inc.
GS881E18B(T/D)/GS881E 32B(D)/GS881E36B(T/D)
GS881E36B 100-Pin TQFP Pinout
DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 E2 BD BC BB BA A 17 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9
LBO A5 A4 A3 A2 A1 A0 TMS TDI VSS VDD Rev: 1.00b 12/2002 3/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TDO TCK A10 A11 A12 A13 A14 A15 A16 © 2001, Giga Semiconductor, Inc.
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