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Details, datasheet, quote on part number:GS88218AB-225
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Datasheet text preview:
GS88218/36AB/D-250/225/200/166/150/133 119- and 165-Bump BGA Commercial Temp Industrial Temp Features
512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
Flow Through/Pipeline Reads
250 MHz133MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
· FT pin for user-configurable flow through or pipeline operation · Single/Dual Cycle Deselect selectable · IEEE 1149.1 JTAG-compatible Boundary Scan · On-chip read parity checking; even or odd selectable · ZQ mode pin for user-selectable high/low output drive · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to SCD x18/x36 Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 119- and 165-bump BGA packages
either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V
tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36)
-250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 280 330 275 320 5.5 5.5 175 200 175 200 255 300 250 295 6.0 6.0 165 190 165 190 230 270 230 265 6.5 6.5 160 180 160 180 200 230 195 225 7.0 7.0 150 170 150 170 185 215 180 210 7.5 7.5 145 165 145 165 165 190 165 185 8.5 8.5 135 150 135 150 mA mA mA mA ns ns mA mA mA mA
The GS88218/36A is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Byte Write and Global Write
FLXDriveTM
Functional Description
Applications
The GS88218/36A is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
Controls
The GS88218/36A operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Rev: 1.03a 9/2002
1/38
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS88218/36AB/D-250/225/200/166/150/133 165 Bump BGA--x18 Commom I/O--Top View (Package D)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQB NC LBO 2 A A NC DQB DQB DQB DQB MCL NC NC NC NC SCD NC NC 3 E1 E2 VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A A 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC A1 A0 7 BW GW VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC TDO TCK 8 ADSC G VS S VD D VD D VD D VD D VD D VD D VD D VD D VD D VS S A A 9 ADV ADSP VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A A 10 A A NC NC NC NC NC ZQ DQA DQA DQA DQA NC A A 11 A18 NC DQA DQA DQA DQA DQA ZZ NC NC NC NC NC A17 A A B C D E F G H J K L M N P R
11 x 15 Bump BGA--13mm x 15 mm Body--1.0 mm Bump Pitch
Rev: 1.03a 9/2002
2/38
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88218/36AB/D-250/225/200/166/150/133 165 Bump BGA--x36 Common I/O--Top View (Package D)
1 A B C D E F G H J K L M N P R NC NC DQC DQC DQC DQC DQC FT DQD DQD DQD DQD DQD NC LBO 2 A A NC DQC DQC DQC DQC MCL DQD DQD DQD DQD SCD NC NC 3 E1 E2 VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC A1 A0 7 BW GW VS S VS S VS S VS S VS S VS S VS S VS S VS S VS S NC TDO TCK 8 ADSC G VS S VD D VD D VD D VD D VD D VD D VD D VD D VD D VS S A A 9 ADV ADSP VD D Q VD D Q VD D Q VD D Q VD D Q NC VD D Q VD D Q VD D Q VD D Q VD D Q A A 10 A A NC DQB DQB DQB DQB ZQ DQA DQA DQA DQA NC A A 11 NC NC DQB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQA A17 A A B C D E F G H J K L M N P R
11 x 15 Bump BGA--13mm x 15 mm Body--1.0 mm Bump Pitch
Rev: 1.03a 9/2002
3/38
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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