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Details, datasheet, quote on part number:GS882Z18AD-150I
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Datasheet text preview:
GS882Z18/36AB/D-250/225/200/166/150/133 119 and 165 BGA Commercial Temp Industrial Temp Features
· NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · 2.5 V or 3.3 V +10%/10% core power supply · 2.5 V or 3.3 V I/O supply · User-configurable Pipeline and Flow Through mode · ZQ mode pin for user-selectable high/low output drive · IEEE 1149.1 JTAG-compatible Boundary Scan · On-chip parity encoding and error detection · LBO pin for Linear or Interleave Burst mode · Pin-compatible with 2M, 4M, and 8M devices · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · ZZ Pin for automatic power-down · JEDEC-standard 119-bump BGA and 165-bump FPBGA packages Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) tK Q tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 280 330 275 320 5.5 5.5 175 200 175 200 255 300 250 295 6.0 6.0 165 190 165 190 230 270 230 265 6.5 6.5 160 180 160 180 200 230 195 225 7.0 7.0 150 170 150 170 185 215 180 210 7.5 7.5 145 165 145 165 165 190 165 185 8.5 8.5 135 150 135 150 mA mA mA mA ns ns mA mA mA mA
9Mb Pipelined and Flow Through Synchronous NBT SRAM
Functional Description
250 MHz133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
The GS882Z18/36A is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS882Z18/36A may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS882Z18/36A is implemented with GSI's high performance CMOS technology and is available in JEDECstandard 119-bump BGA and 165-bump FPBGA packages.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock Address Read/Write
A R
B W QA
C R DB QA
D W QC DB
E R DD QC
F W QE DD QE
Flow Through Data I/O Pipelined Data I/O
Rev: 1.02a 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/35
© 2001, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS882Z18/36AB/D-250/225/200/166/150/133 GS882Z36A Pad Out
119 Bump BGA--Top View (Package B)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC D QC 4 D QC 3 VDDQ D QC 2 D QC 1 VDDQ D QD 1 D QD 2 VDDQ D QD 3 D QD 4 NC NC VDDQ 2 A6 E2 A5 D QC 9 D QC 8 D QC 7 D QC 6 D QC 5 VD D D QD 5 D QD 6 D QD 7 D QD 8 D QD 9 A2 NC TMS 3 A7 A4 A3 VS S VS S VS S BC VS S NC VS S BD VS S VS S VS S LBO A1 0 TDI 4 NC ADV VD D ZQ E1 G A1 7 W VD D CK NC CKE A1 A0 VD D A11 TCK 5 A8 A15 A 14 VSS VS S VS S BB VS S NC VS S BA VS S VS S VS S FT A 12 TDO 6 A9 E3 A 16 D QB 9 D QB 8 D QB 7 D QB 6 D QB 5 VD D D QA 5 D QA 6 D QA 7 D QA 8 D QA 9 A 13 NC NC 7 VD D Q NC NC D QB 4 D QB 3 VD D Q D QB 2 D QB 1 VD D Q D QA 1 D QA 2 VD D Q D QA 3 D QA 4 PE ZZ VDDQ
Rev: 1.02a 9/2002
2/35
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS882Z18/36AB/D-250/225/200/166/150/133 GS882Z18A Pad Out
119 Bump BGA--Top View (Package B)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC D QB 1 NC VDDQ NC D QB 4 VDDQ NC D QB 6 VDDQ D QB 8 NC NC NC VDDQ 2 A6 E2 A5 NC DQB2 NC DQB3 NC VD D DQB5 NC D QB 7 NC DQB9 A2 A1 0 TMS 3 A7 A4 A3 VS S VS S VS S BB VS S NC VS S NC VS S VS S VS S LBO A11 TDI 4 NC ADV VD D ZQ E1 G A1 7 W VD D CK NC CKE A1 A0 VD D NC TCK 5 A8 A 15 A 14 VSS VS S VS S NC VS S NC VS S BA VS S VS S VS S FT A 12 TDO 6 A9 E3 A 16 D QA 9 NC D QA 7 NC D QA 5 VD D NC D QA 3 NC D QA 2 NC A 13 A 18 NC 7 VD D Q NC NC NC DQA8 VD D Q DQA6 NC VD D Q DQA4 NC VD D Q NC DQA1 PE ZZ VDDQ
Rev: 1.02a 9/2002
3/35
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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