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Details, datasheet, quote on part number:GS882Z18B-66I
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Datasheet text preview:
Preliminary GS882Z18/36B-11/100/80/66 119-Bump BGA Commercial Temp Industrial Temp Features
· 512K x 18 and 256K x 36 configurations · User-configurable Pipelined and Flow Through mode · NBT (No Bus Turn Around) functionality allows zero wait · Read-Write-Read bus utilization · Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs · IEEE 1149.1 JTAG-compatible Boundary Scan · On-chip write parity checking; even or odd selectable · ZQ mode pin for user selectable high/low output drive strength. · x16/x32 mode with on-chip parity encoding and error detection · Pin-compatible with 2M, 4M and 16M devices · 3.3 V +10%/5% core power supply · 2.5 V or 3.3 V I/O supply · LBO pin for Linear or Interleave Burst mode · Byte write operation (9-bit Bytes) · 3 chip enable signals for easy depth expansion · Clock Control, registered, address, data, and control · ZZ Pin for automatic power-down · JEDEC-standard 119-Bump BGA package -11 Pipeline 3-1-1-1 Flow Through 2-1-1-1 tC y c l e tK Q ID D tK Q tC y c l e ID D 10 ns 4.5 ns 210 mA 11 ns 15 ns 150 mA -100 10 ns 4.5 ns 210 mA 12 ns 15 ns 150 mA - 80 12.5 ns 4.8 ns 190 mA 14 ns 15 ns 130 mA - 66 15 ns 5 ns 170 mA 18 ns 20 ns 130 mA
8Mb Pipelined and Flow Through 100 MHz66 MHz 3.3 V VDD Synchronous NBT SRAMs 2.5 V and 3.3 V VDDQ
Functional Description
The GS882Z818/36B is an 8Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS882Z818/36B may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS882Z818/36B is implemented with GSI's high performance CMOS technology and is available in a JEDECStandard 119-bump BGA package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock Address Read/Write
A R
B W QA
C R DB QA
D W QC DB
E R DD QC
F W QE DD QE
Flow Through Data I/O Pipelined Data I/O
Rev: 1.15 6/2001
1/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary. GS882Z18/36B-11/100/80/66 GS882Z36 Pad Out
119-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 NC NC VDDQ
2
A6 E2 A5 DQPC9 DQC8 DQC7 DQC6 DQC5 VDD DQD5 DQD6 DQD7 DQD8 DQPD9 A2 NC TMS
3
A7 A4 A3 VSS VSS VSS BC VSS DP VSS BD VSS VSS VSS LBO A10 TDI
4
NC ADV VDD ZQ E1 G A17 W VDD CK NC CKE A1 A0 VDD A11 TCK
5
A8 A15 A14 VSS VSS VSS BB VSS QE VSS BA VSS VSS VSS FT A12 TDO
6
A9 E3 A16 DQPB9 DQB8 DQB7 DQB6 DQB5 VDD DQA5 DQA6 DQA7 DQA8 DQPA9 A13 NC NC
7
VDDQ NC NC DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA1 DQA2 VDDQ DQA3 DQA4 PE ZZ VDDQ
Rev: 1.15 6/2001
2/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary. GS882Z18/36B-11/100/80/66 GS882Z18 Pad Out
119-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQB1 NC VDDQ NC DQB4 VDDQ NC DQB6 VDDQ DQB8 NC NC NC VDDQ
2
A6 E2 A5 NC DQB2 NC DQB3 NC VDD DQB5 NC DQB7 NC DQB9 A2 A10
3
A7 A4 A3 VSS VSS VSS BB VSS DP VSS NC VSS VSS VSS LBO A11
4
NC ADV VDD ZQ E1 G A17 W VDD CK NC CKE A1 A0 VDD NC
5
A8 A15 A14 VSS VSS VSS NC VSS QE VSS BA VSS VSS VSS FT A12
6
A9 E3 A16 DQA9 NC DQA7 NC DQA5 VDD NC DQA3 NC DQA2 NC A13 A18 NC
7
VDDQ NC NC NC DQA8 VDDQ DQA6 NC VDDQ DQA4 NC VDDQ NC DQA1 PE ZZ VDDQ
Rev: 1.15 6/2001
3/34
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
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