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Part: M37544M2-XXXSP
Category:
Microprocessors
-> 8 bit
-> 740 family->740 series
Description:
Company: Renesas
Datasheet: Download M37544M2-XXXSP datasheet File size : 684 kB
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Datasheet text preview:
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
7544 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0012-0101Z Rev.1.01 2003.05.06
DESCRIPTION
The 7544 Group is the 8-bit microcomputer based on the 740 family core technology. The 7544 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an A-D converter, and is useful for control of home electric appliances and office automation equipment.
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FEATURES
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Basic machine-language instructions ..... 71 The minimum instruction execution time ....... 0.25 µs ( a t 8 MHz oscillation frequency, double-speed mode for the shortest instruction) Memory size ROM ......... 8 K bytes RAM ........ 256 bytes Programmable I/O ports .. 25 Interrupts ....... 12 sources, 12 vectors Timers ........... 8-bit 2 ..... 16-bit 1 Serial I/O .... 8-bit 1 (UART or Clock-synchronized) A-D converter ....... 8-bit 6 channels
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Clock generating circuit ............ Built-in type (low-power dissipation by a ring oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation) Watchdog timer ... 16-bit 1 Power source voltage XIN oscillation frequency at ceramic/quartz-crystal oscillation, in double-speed mode At 8 MHz ........... 4.5 to 5.5 V XIN oscillation frequency at ceramic/quartz-crystal oscillation, in high-speed mode At 8 MHz ........... 4.0 to 5.5 V XIN oscillation frequency at RC oscillation At 4 MHz ........... 4.0 to 5.5 V Power dissipation .......... 22.5mW(standard) Operating temperature range .. 20 to 85 °C
APPLICATION
O ff i c e automation equipment, factory automation equipment, home electric appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
P12/SCLK P13/SRDY P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VC C XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P11/TXD P10/RXD P07(LED7) P06(LED6) P05(LED5) P04(LED4) P03(LED3)/TXOUT P02(LED2) P01(LED1) P00(LED0)/CNTR1 P37(LED13)/INT0 P34(LED12)/INT1 P33(LED11) P32(LED10) P31(LED9) P30(LED8)
Package type : 32P4B
Fig. 1 Pin configuration (32P4B type)
M37544M2-XXXSP M37544G2SP
Rev.1.01
2003.05.06
page 1 of 53
PRELIMINARY
7544 Group
Notice: This is not a final specification. Some parametric limits are subject to change.
20
22
24
21
19
P07(LED7) P10/RXD P11/TXD P12/SCLK P13/SRDY P14/CNTR0 P20/AN0 P21/AN1
23
18
17
P06(LED6) P05(LED5) P04(LED4) P03(LED3)/TXOUT P02(LED2) P01(LED1) P00(LED0)/CNTR1 P37(LED13)/INT0
25 26 27 28 29 30 31 32
1 3 2 4 5 6 7 8
16 15 14
M37544M2-XXXGP M37544G2GP
13 12 11 10 9
P34(LED12)/INT1 P33(LED11) P32(LED10) P31(LED9) P30(LED8) VSS XOUT XIN
Package type : 32P6U-A
Fig. 2 Pin configuration (32P6U-A type)
P14/CNTR0 NC NC P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 NC NC NC NC VREF RESET CNVSS Vcc XIN XOUT VSS
P22/AN2 P23/AN3 P24/AN4 P25/AN5 VR E F RESET CNVSS VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P13/SRDY P12/SCLK P11/TXD P10/RXD P07(LED7) P06(LED6) P05(LED5) P04(LED4) P03(LED3)/TXOUT P02(LED2) P01(LED1) P00(LED0)/CNTR1 NC P37(LED13)/INT0 NC NC P34(LED12)/INT1 P33(LED11) P32(LED10) P31(LED9) P30(LED8)
Outline 42S1M
Fig. 3 Pin configuration (42S1M type)
M37544RSS
Rev.1.01
2003.05.06
page 2 of 53
FUNCTIONAL BLOCK
Key-on wakeup
Fig. 4 Functional block diagram (32P4B package)
Rev.1.01
VSS VCC CNVSS
12 13 11 16
7544 Group
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
Clock input X IN
Clock output X OUT
Reset input RESET
2003.05.06
CPU
14
15
page 3 of 53
Clock generating circuit
RAM
A Prescaler 1 (8) X Y S
CNTR0
ROM
Timer 1 (8)
Prescaler X (8)
Timer X (8)
TXOUT
PCH PS
PCL Timer A (16)
CNTR1
Watchdog timer
Reset
0
A-D converter (8) SI/O(8)
INT0 INT1
PRELIMINARY
P3(6) P2(6)
P1(5)
P0(8)
10
22 21 20 19 18 17
987654
3 2 1 32 31
30 29 28 27 26 25 24 23
V REF
Notice: This is not a final specification. Some parametric limits are subject to change.
I/O port P3
I/O port P2
I/O port P1
I/O port P0
Others parts begin by m3
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