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Part: M5M5408BTP-70HI
Category:
Memory
-> SRAM
-> Low Power
Description:
Company: Renesas
Datasheet: Download M5M5408BTP-70HI datasheet File size : 484 kB
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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
revision-2.0e, Feb.12, 2002
M I TSUBISHI LSIs
M5M5408BFP/TP/RT
4 1 9 4 3 0 4 - B I T (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5408B is a f amily of 4-Mbit static RAMs organized as 524,288-words by 8-bit, f abricated by Mitsubishi's highperf ormance 0.25µm CMOS technology . The M5M5408B is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv e s . M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic TSOP. Two ty pes of TSOPs are av ailable, M5M5408BTP (normal-lead-bend TSOP) , M5M5408BRT (rev erse-lead-bend TSOP). These two ty pes TSOPs are suitable f or a surf a c e mounting on double-sided printed circuit boards. From the point of operating temperature, the f amily is div ided into two v ersions; "Standard" and "I-v ersion". Those are · · · · · · · · · · ·
FEATURES
Single +5V power supply Small stand-by current: 0.4µA(3V,ty p . ) No clocks, No ref r e s h Data retention supply v oltage=2.0V to 5.5V All inputs and outputs are TTL compatible. Easy memory expansion by S# Common Data I/O Three-state outputs: OR-tie capability OE# prev ents data contention in the I/O bus Process technology : 0.25µm CMOS Package: M5M5408BFP: 32 pin 525 mil SOP M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
PART NAME TABLE
Version, Operating temperature Part name (## stands f or "FP","TP",and "RT") M 5 M 5 4 0 8 B # # -55H M 5 M 5 4 0 8 B # # -70H M 5 M 5 4 0 8 B # # -55HI M 5 M 5 4 0 8 B # # -70HI
Power Supply
5 . 0V 5 . 0V
Access time
Stand-by c urrent Icc(PD), Vcc=3.0V t y p ical * 25°C 0.4µA 0.4µA 25 ° C 1µA 1µA Limit s (max.) 70°C 15 µA 15 µA 85°C --30 µA
max.
55 ns 70 ns 55 ns 70 ns
Activ e current Icc1 ( 5 . 0 V , ty p . * ) 50 m A (10MHz) 25 m A (1MHz)
Standard 0 ~ +70°C I-v ersion -40 ~ +85°C
*Ty pical v alues are sampled, and are not 100% tested.
PIN CONFIGURATION (TOP VIEW)
A 18 A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ 1 DQ 2 DQ 3 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A 15 A 17 W# A 13 A8 A9 A 11 OE# A 10 S# DQ 8 DQ 7 DQ 6 DQ 5 DQ 4
VCC A 15 A 17 W# A 13 A8 A9 A 11 OE# A 10 S# DQ 8 DQ 7 DQ 6 DQ 5 DQ 4
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A 18 A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 DQ 1 DQ 2 DQ3 GND
Pin A0 ~ A18 S# ( S ) W# ( W ) OE# (OE) Vcc GND
Function Address input Chip select input Write control input Output inable input Power supply Ground supply
DQ1 ~ DQ8 Data input / output
O u t l i n e 32P2M-A (FP) 32P3Y-H (TP)
Outline
32P3Y-J (RT)
1
revision-2.0e, Feb.12, 2002
M I TSUBISHI LSIs
M5M5408BFP/TP/RT
4 1 9 4 3 0 4 - B I T (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5408BFP,TP,RT is organized as 524,288-words by 8-bit. These dev ices operate on a single +5.0V power supply , and are directly TTL compatible to both input and o u t p u t . Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. A write operation is executed during the S# low and W# low ov erlap time. The address(A0~A18) must be set up bef ore the write cy c le A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while S# are in an activ e state (S#=L). When setting S# at a high lev el, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips. Setting the OE# at a high lev el,the output stage is in a highimpedance state, and the data bus contention problem in the write cy c le is eliminated. The power supply c urrent is reduced as low as 0.4µA ( 2 5 ° C , ty pical), and the memory data can be held at +2V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. Pin Mode Non selection Write Read DQ High-impedance D a t a input (D) Data output (Q) Icc Standby Activ e Activ e Activ e A0 ~ A18 S# ( S ) W# ( W ) OE# (OE) Vcc GND Function Address input Chip select input Write control input Output inable input Power supply Ground supply
FUNCTION TABLE
S# H L L L W# X L H H OE# X X L H
DQ1 ~ DQ8 Data input / output
High-impedance Read note: "H" and "L" in this table mean VIH and VIL, respectiv ely . "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A4 A5 A6 A7 A 12 A 14 A 16 A 17 A 18 A 15 A 10 A 11 A9 A8 A 13
8 7 6 5 4 3 2 30 1 31 13 14
MEMORY ARRAY 524288 WORDS x 8 BITS
15 17 18 19 20 21
D Q1 D Q2 D Q3 D Q4 D Q5 D Q6 D Q7 D Q8
23 25 26 27 28 29 22 24
CLOCK GENERATOR
W# S# OE# V CC
(5V)
A0 A1 A2 A3
12 11 10 9
32
16
GND
(0V)
2
Others parts begin by m5
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