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Details, datasheet, quote on part number:HT46R24
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| Part: | HT46R24 |
| Category: | Microcontrollers => 8 bit |
| Description: | A/D Type 8-Bit MCU <<<>>>General Description <<<>>>The HT46R24/HT46C24 Are 8-bit, High Performance, Risc Architecture Microcontroller Devices Specifically Designed For A/D Applications That Interface Directly to Analog Signals, Such as Those From Sensors. The Mask Version HT46C24 is Fully Pin And Functionally Compatible With The OTP Version HT46R24 Device.<<<>>><<<>>>the Advantages of Low Power Consumption, I/o Flexibility, Programmable Frequency Divider, Timer Functions, Oscillator Options, Multi-channel A/D Converter, Pulse Width Modulation Function, I2C Interface, Halt And Wake-up Functions, Enhance The Versatility of These Devices to Suit a Wide Range of A/D Application Possibilities Such as Sensor Signal Processing, Motor Driving, Industrial Control, Consumer Products, Subsystem Controllers, Etc. |
| Company: | Holtek Semiconductor Inc. |
| Datasheet: | Download HT46R24 datasheet File size : 403 kB |
| Request For quote: | Find where to buy HT46R24
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Datasheet text preview:
HT46R24/HT46C24 A/D Type 8-Bit MCU
Features
· Operating voltage: · Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
· 40 bidirectional I/O lines (max.) · 1 interrupt input shared with an I/O line · Two 16-bit programmable timer/event counter with
at VDD=5V
· 16-level subroutine nesting · 8 channels 10-bit resolution A/D converter · 4-channel 8-bit PWM output shared with
four I/O lines
· Bit manipulation instruction · 16-bit table read instruction · 63 powerful instructions · All instructions in one or two machine cycles · Low voltage reset function · I2C Bus (slave mode) · 28-pin SKDIP/SOP, 48-pin SSOP package
overflow interrupt
· On-chip crystal and RC oscillator · Watchdog Timer · 8192´16 program memory · 384´8 data memory RAM · Supports PFD for sound generation · HALT function and wake-up feature reduce power
consumption
General Description
The HT46R24/HT46C24 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The mask version HT46C24 is fully pin and functionally compatible with the OTP version HT46R24 device. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, I2C interface, HALT and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc.
I2C is a trademark of Philips Semiconductors.
Rev. 1.50
1
May 3, 2004
HT46R24/HT46C24
Block Diagram
In te rru p t C ir c u it STACK P ro g ra m EPROM P ro g ra m C o u n te r IN T C TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 M U X M U X P r e s c a le r TM R0 TM R1 fS
YS
fS
YS
/4
BP In s tr u c tio n R e g is te r MP M U X
WDT
DATA M e m o ry
M U
fS X
YS
/4
W DT OSC PF0~PF7
PFC PF
P o rt F
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX
PA5
PW PDC
M
P o rt D
STATUS
PD
P D 0 /P W M 0 ~ P D 3 /P W PD 4~PD 7
M3
S h ifte r
PCC PC
P o rt C
PC 0~PC7
8 -C h a n n e l A /D C o n v e rte r OSC2 OS RE VD VS S S D C1 ACC H ALT LVR E N /D IS PBC PB PAC PA IC Bus S la v e M o d e
2
P o rt B
P B 0 /A N 0 ~ P B 7 /A N 7 PA PA PA PA PA PA 0~ 3/ 4 5/ 6/ 7/ PA2 PFD IN T SDA SCL
P o rt A
Pin Assignment
P B 5 /A N 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P B 4 /A N 4 P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 P B 5 /A N 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P B 4 /A N 4 P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS PC0 PC1 PC2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P B 6 /A N 6 P B 7 /A N 7 PA4 P A 5 /IN T P A 6 /S D A P A 7 /S C L OSC2 OSC1 VDD RES P D 1 /P W M 1 /T M R 1 P D 0 /P W M 0 PC4 PC3 NC PF3 PF2 PF1 PD7 PD6 PD5 PD4 VSS PF0 TM R0 PC0 PC1 PC2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P B 6 /A N 6 P B 7 /A N 7 PA4 P A 5 /IN T P A 6 /S D A P A 7 /S C L PF4 PF5 PF6 PF7 OSC2 OSC1 VDD RES TM R1 P D 3 /P W M 3 P D 2 /P W M 2 P D 1 /P W M 1 P D 0 /P W M 0 PC7 PC6 PC5 PC4 PC3
H T 4 6 R 2 4 /H T 4 6 C 2 4 2 8 S K D IP -A /S O P -A
H T 4 6 R 2 4 /H T 4 6 C 2 4 4 8 S S O P -A
Rev. 1.50
2
May 3, 2004
HT46R24/HT46C24
Pad Assignment
HT46C24
P A 6 /S D A P A 3 /P F D P B 4 /A N 4 P B 5 /A N 5 P B 6 /A N 6 P B 7 /A N 7 P A 7 /S C L P A 5 /IN T
PA4
PA0 54
PA1 53
PA2 52
PF4
51
50
49
48
47
46
45
44
43
42
41 40 39 38
PF5 PF6 PF7 OSC2
P B 3 /A N 3 1 2 3 4 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0
(0 ,0 ) 37 5 6 7 34 9 33 32 31 30 14 GND 15 PF0 16 TM R0 17 PC0 18 PC1 19 PC2 20 PC3 21 PC4 22 PC5 23 PC6 24 PC7 25 P D 0 /P W M 0 26 P D 1 /P W M 1 27 TEST1 28 TEST2 29 TEST3
OSC1 VCC 35 VCC VCC RES TM R1 P D 3 /P W M 3 P D 2 /P W M 2
PF3 PF2 PF1 PD7 8 PD6 PD5 PD4 GND GND
36
10 11 12 13
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pin Description
Pin Name PA0~PA2 PA3/PFD PA4 PA5/INT PA6/SDA PA7/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 I/O Options Pull-high Wake-up PA3 or PFD I/O or Serial Bus Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by option (bit option). Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). The PFD and INT are pin-shared with PA3 and PA5, respectively. Once the I2C Bus function is used, the internal registers related to PA6 and PA7 cannot be used.
I/O
I/O
Pull-high
Bidirectional 8-bits input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are automatically disabled.
Rev. 1.50
3
May 3, 2004
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