|
Details, datasheet, quote on part number:HX6156
| |
Datasheet text preview:
Aerospace Electronics
Advance Information
256K x 1 STATIC RAM--SOI
FEATURES
RADIATION · Fabricated with RICMOSTM IV Silicon on Insulator (SOI) 0.75 µm Process (Leff = 0.6 µm) · Total Dose Hardness through 1x106 rad(SiO2) · Neutron Hardness through 1x1014 cm-2 · Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s · Dose Rate Survivability through 1x1011 rad(Si)/s · Soft Error Rate of <1x10-10 upsets/bit-day in Geosynchronous Orbit OTHER · Fast Read/Write Cycle Times 15 ns (Typical) 25 ns (-55 to 125°C) · Asynchronous Operation · CMOS or TTL Compatible I/O · Single 5 V ± 10% Power Supply
HX6156
· Packaging Options 24-Lead Flat Pack (0.540 in. x 0.600 in.) 28-LeadFlat Pack (0.500 in. x 0.720 in.)
GENERAL DESCRIPTION
The 256K x 1 Radiation Hardened Static RAM is a high performance 262,144 word x 1-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell's radiation hardened technology, and is designed for use in systems operating in radiation environments. The RAM operates over the full military temperature range and requires only a single 5 V ± 10% power supply. The RAM is available with either TTL or CMOS compatible I/O. Power consumption is typically less than 15 mW/MHz in operation, and less than 5 mW when de-selected. The RAM read operation is fully asynchronous, with an associated typical access time of 15 ns at 5 V. Honeywell's enhanced SOI RICMOSTM IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques. The RICMOSTM IV process is a 5-volt, SIMOX CMOS technology with a 150 Å gate oxide and a minimum drawn feature size of 0.75 µm (0.6 µm effective gate length--Leff). Additional features include tungsten via plugs, Honeywell's proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability. A 7 transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power bussing and the low collection volume SIMOX substrate provide improved dose rate hardening.
HX6156
FUNCTIONAL DIAGRAM
A:0-2, 5, 13-17 Row Decoder
· · ·
9
262,144 x 1 Memory Array
· · ·
CE* NCS
Column Decoder Data Input/Output NWE
WE · CS · CE
1 1
D Q
NOE*
NWE · CS · CE · OE (0 = high Z)
1 = enabled Signal # Signal
A:3-4, 6-12
9
All controls must be enabled for a signal to pass. (#: number of buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-17 NCS Address input pins which select a particular bit within the memory array. Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS forces the SRAM to a precharge condition, holds the data output driver in a high impedance state and disables all input buffers except CE. If this signal is not used it must be connected to VSS. Negative write enable, when at a low level activates a write operation and holds the data output driver in a high impedance state. When at a high level NWE allows normal read operation. Negative output enable, when at a high level holds the data output driver in a high impedance state. When at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be connected to VSS. Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a precharge condition, holds the data output driver in a high impedance state and disables all the input buffers except the NCS input buffer. If this signal is not used it must be connected to VDD. Data input pin during a write operation. Remains in the high impedance state during a read operation. Data output pin during a read operation. Remains in the high impedance state during a write operation.
NWE NOE*
CE*
D Q
TRUTH TABLE
NCS L L H X CE* H H X L NWE H L XX XX NOE* L X XX XX MODE Read Write Deselected Disabled D X Data In XX XX Q Data Out High Z High Z High Z
Notes: X: VI=VIH or VIL XX: VSSVIVDD NOE=H: High Z output state maintained for NCS=X, CE=X, NWE=X
*Available in 28-pin package only. 2
HX6156
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose The SRAM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T =125°C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 keV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. The SRAM will meet any functional or electrical specification after exposure to a radiation pulse up to the transient dose rate survivability specification, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects.
Neutron Radiation The SRAM will meet any functional or timing specification after exposure to the specified neutron fluence under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV.
Transient Pulse Ionizing Radiation The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse up to the transient dose rate upset specification, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation is 10%), it is suggested that stiffening capacitance be placed on or near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through or valid stored data requirements, typical circuit board mounted de-coupling capacitors are recommended.
Soft Error Rate The SRAM has an extremely low Soft Error Rate (SER) as specified in the table below. This hardness level is defined by the Adams 90% worst case cosmic ray environment. The low SER is achieved by the use of a unique 7-transistor memory cell and the oxide isolation of the SOI substrate.
Latchup The SRAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SIMOX substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs.
RADIATION HARDNESS RATINGS (1)
Parameter Total Dose Transient Dose Rate Upset Transient Dose Rate Survivability Soft Error Rate (SER) Neutron Fluence Limits (2) 1x106 1x109 1x1011 <1x10-10 1x10
14
Units rad(SiO2) rad(Si)/s rad(Si)/s upsets/bit-day N/cm2
Test Conditions
TA=25°C Pulse width 1 µs Pulse width 50 ns, X-ray, VDD=6.0 V, TA=25°C TA=125°C, Adams 90% worst case environment 1 MeV equivalent energy, Unbiased, TA=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions. (2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.
3
|
|
