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Details, datasheet, quote on part number:HX6218
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Datasheet text preview:
Aerospace Electronics
FIFO--SOI
FEATURES
· 1K x 36, 2K x 18, 4K x 9 Organizations · Fabricated with RICMOSTM IV Silicon on Insulator (SOI) 0.8 µm Process (Leff = 0.65µm) RADIATION OTHER · Read/Write Cycle Times <35 ns (-55° to 125°C) · Expandable in Width
HX6409 HX6218 HX6136
· Supports Free-Running 50% Duty Cycle Clock · Total Dose Hardness through 1x106 rad(SiO2) · Empty, Full, Half Full, 1/4 Full, 3/4 Full, Error Flags · Neutron Hardness through 1x1014 cm-2 · Parity Generation/Checking · Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s · Dose Rate Survivability through 1x1011 rad(Si)/s · Output Enable (OE) · Soft Error Rate of <1x10-10 upsets/bit-day · CMOS or TTL Compatible I/O · No Latchup · Single 5 V ± 10% Power Supply · Various Flat Pack Options · Fully Asynchronous with Simultaneous Read and Write Operation
GENERAL DESCRIPTION
The HX6409, HX6218, and HX6136 are high speed, lowpower, first-in first-out memories with clocked read and write interfaces. The HX6409 is a 4096 word by 9 bit memory array, the HX6218 is a 2048 word by 18 bit memory array, and the HX6136 is a 1024 word by 36 bit memory array. The FIFOs support width expansion while depth expansion requires external logic control using state machine techniques. Features include programmable parity control, an empty/full flag, a quarter/three quarter full flag, a half full flag and an error flag. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have separate input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free running clock (CKW) and a write enable pin ENW . When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a freerunning read clock (CKR) and a read enable pin (ENR ). In addition, the three FIFOs have an output enable pin (OE ) and a master reset pin (M R ). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 30 MHz are achievable in the three configurations. Honeywell's enhanced SOI RICMOSTM IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques. The FIFO is fabricated with Honeywell's radiation hardened technology, and is designed for use in systems operating in radiation environments. The SOI RICMOSTM IV process is a 5-volt, SIMOX CMOS technology with a 150 Å gate oxide and a minimum drawn feature size of 0.8 µm, (0.65 µm effective gate array--Leff). Additional features include tungsten via plugs, Honeywell's proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability.
Solid State Electronics Center · 12001 State Highway 55, Plymouth, MN 55441 · (800) 323-8295 · http://www.ssec.honeywell.com
HX6409/HX6218/HX6136
LOGIC BLOCK DIAGRAM
D: 0 - 8 D: 0 - 17 D: 0 - 35 Input Register
CKW
ENW Parity Parity Program Register
Write Control HF E/F QF/TQF EF_ Fault
Flag Logic Memory Array 4096 x 9 2048 x 18 1024 x 36
Write Pointer
Read Pointer
MR
Reset Logic Tri-State Output Register Read Control
OE Q: 0 - 8 Q: 0 - 17 Q: 0 - 35
CKR
ENR
FLAG DECODE TABLE
Word Count
EF_ Fa u lt E/ F QF TQ F HF /
State
Empty Fault (Enabled Read when Empty) Empty Less than or Equal to 1/4 Full Less than or Equal to 1/2 Full Greater that 1/2 Full Greater than or Equal to 3/4 Full Full Full Fault (Enabled Write when Full)
4K x 9
0 0 1 to 1024 1025 to 2048 2049 to 3071 3072 to 4095 4096 4096
2K x 18
0 0 1 to 512 513 to 1024 1025 to1535 1536 to 2047 2048 2048
1K x 36
0 0 1 to 256 257 to 512 513 to 767 768 to 1023 1024 1024
0 1 1 1 1 1 1 0
0 0 1 1 1 1 0 0
0 0 0 1 1 0 0 0
1 1 1 1 0 0 0 0
2
HX6409/HX6218/HX6136
SIGNAL DEFINITIONS Signal Name
D: 0 - 35 Q: 0 - 35
I/O
I O
Description
Data Inputs: Data Inputs are written into the FIFO on the rising edge of CKW when ENW is active and the FIFO is not full. Data Outputs: Data Outputs are read out of the FIFO memory and updated on the rising edge of CKR when ENR is active and the FIFO is not Empty. The Data Outputs are in a high impedance state if OE is not active. Enable Write: An active low signal that enables the write of the Data Inputs on the CKW rising edge (if FIFO is not full). Enable Read: An active low signal that enables the read and update of the Data Outputs on the CKR rising edge (if FIFO is not empty). Write Clock: The rising edge clocks data into the FIFO when ENW is low (active). On the rising edge, this signal also updates the Half Full, 3/4 Full, Full, and Full Fault Flags. Read Clock: The rising edge clocks data out of the FIFO when ENR is low (active). On the rising edge, this signal also updates the 1/4 Full, Empty, and Empty Fault Flags. Half Full Flag: Updated on the rising edge of CKW and indicating that the FIFO is greater than half full. Empty or Full Flag: Empty is updated on the rising edge of CKR, and Full is updated on the rising edge of CKW. 1/4 Full or 3/4 Full Flag: 1/4 Full is updated on the rising edge of CKR, and 3/4 Full is updated on the rising edge of CKW. 1/4 Full signifies 256 or less words in the 1K x 36 FIFO and 3/4 Full signifies 256 words or less until a full condition. Empty or Full Fault Flag: empty Fault is updated on the rising edge of CKR, and Full Fault is updated on the rising edge of CKW. Empty Fault signifies a read to an already empty FIFO, and Full Fault signifies a write to an already full FIFO. Once a fault condition is detected, the Fault Flag remains latched until the empty or full condition is removed. Master Reset: Active low signal which, when active, resets device to empty condition. Output Enable: Active low signal which, when active, enables low impedance Data Outputs, Q: 0 - 35.
ENW
I I I I O O O
ENR
CKW CKR
HF
E/ F QF/TQF
EF_ Fault
O
MR O E
I I
PROGRAMMABLE PARITY OPTIONS
D2
O I I I I
D1
X O O I I
D0
X O I O I
Conditions
Parity Disabled Generate Even Parity, Q8, Q17, Q26, Q35 Generate Odd Parity, Q8, Q17, Q26, Q35 Check for Even Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal Check for Odd Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal
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