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Details, datasheet, quote on part number:HX6408
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Datasheet text preview:
Aerospace Electronics
Advance Information
512K x 8 STATIC RAM--SOI
FEATURES
RADIATION · Fabricated with RICMOSTM V Silicon On Insulator (SOI) 0.35 µm Process (Leff = 0.28 µm) · Total Dose Hardness 3x105 rad(SiO2) (Optional 1X106 rad(SiO2) · Neutron Hardness 1x1014 cm-2 · Dynamic and Static Transient Upset Hardness 1x1010 rad(Si)/s (3.3 V) · Dose Rate Survivability 1x1012 rad(Si)/s · Soft Error Rate Upsets/bit-day 1x10-10 (3.3 V) · No Latchup OTHER · Read/Write Cycle Times 20 ns, (3.3 V), 0 to 80°C 25 ns, (3.3 V), -55 to 125°C · Typical Operating Power 9.5 mW/MHz (3.3 V) · Asynchronous Operation · CMOS Compatible I/O · Single Power Supply, 3.3 V ± 0.3 V · Operating Range is -55°C to +125°C · Package Options: 36-Lead Flat Pack · Optional Low Power Sleep Mode
HX6408
GENERAL DESCRIPTION
The 512K x 8 Radiation Tolerant Static RAM is a high performance 524,288 word x 8-bit static random access memory with optional industry-standard functionality. It is fabricated with Honeywell's radiation hardened technology, and is designed for use in low voltage systems operating in radiation environments. The RAM operates over the full military temperature range and requires only a single 3.3 V ± 0.3V power supply. Power consumption is typically less than 9.5 mW/MHz in operation, and less than 6 mW when de-selected. Honeywell's enhanced SOI RICMOSTM V (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques. The RICMOSTM V low power process is a SIMOX CMOS technology with a 80 Å gate oxide and a minimum drawn feature size of 0.35 µm. Additional features include tungsten via and contact plugs, Honeywell's proprietary SHARP planarization process and a lightly doped drain (LDD) structure for improved short channel reliability. A seven transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power busing and the low collection volume SIMOX substrate provide improved dose rate hardening.
Solid State Electronics Center · 12001 State Highway 55, Plymouth, MN 55441 · (800) 238-1502 · http://www.ssec.honeywell.com
HX6408
FUNCTIONAL DIAGRAM
A d d re s s Decoder
An
Memory Array
8 NWE DQ:0-7
Timing / Control
8
WE · CS
NSL
1 = enabled Signal # Signal
NCS NOE
NWE · CS
All controls must be enabled for a signal to pass. (#: number of buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-18 DQ: 0-7 NCS Address input pins which select a particular eight-bit word within the memory array. Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state. If this signal is not used it must be connected to VSS. Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level NWE allows normal read operation. Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NWE and NSL. If this signal is not used it must be connected to VSS. This signal is asynchronous. Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the NCS and NOE input buffers. If this signal is not used it must be connected to VDD. This signal is asynchronous. The HX6408 may be ordered without the sleep mode option and pin 36 is then a NC.
NWE NOE
NSL
TRUTH TABLE
NCS L L H X NS L H H X L N WE H L X X NO E L X X X Mo d e Re ad Write De se le cte d S le e p DQ Data Out Data In Hig h Z Hig h Z
X: VI=VIH or VIL, NOE=H: High Z output state maintained for NCS=X, CE=X, NWE=X
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HX6408
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose The SRAM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 3.6 V and T =125°C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 KeV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 KeV X-rays applied at a dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. Transient Pulse Ionizing Radiation The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse, up to the specified transient dose rate upset specification, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation is 10%), it is suggested that stiffening capacitance be placed near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operatethrough or valid stored data requirements, typical circuit board mounted de-coupling capacitors are recommended. The SRAM will meet any functional or electrical specificaThe SRAM is capable of meeting the specified Soft Error Rate (SER), under recommended operating conditions. This hardness level is defined by the Adams 90% worst case cosmic ray environment for geosynchronous orbits. Latchup The SRAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SIMOX substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs. tion after exposure to a radiation pulse up to the transientdose rate survivability specification, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects. Neutron Radiation The SRAM will meet any functional or timing specification after exposure to the specified neutron fluence under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. Soft Error Rate
RADIATION HARDNESS RATINGS (1)
Parameter Total Dose Transient Dose Rate Upset Transient Dose Rate Survivability Soft Error Rate Neutron Fluence Limits (2) 3x105 (Optional 1X106) 1x1010 1x1012 <1x10-10 1x1014 Units rad(SiO2) rad(Si)/s rad(Si)/s upsets/bit-day N/cm 2 Test Conditions
TA=25°C Pulse width 50 ns VDD>3.6V, TA=25°C Pulse width 50 ns, X-ray, VDD=3.6 V, TA=25°C TA=85°C, Adams 90% worst case environment 1 MeV equivalent energy, Unbiased, TA=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions. (2) Operating conditions (unless otherwise specified): VDD=3.0 V to 3.6 V, TA=-55°C to 125°C.
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