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Details, datasheet, quote on part number:HX84050
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Datasheet text preview:
Military & Space Products
5 MEGABIT MEMORY MODULE
HX84050
RADIATION · Fabricated with RICMOSTM IV Silicon on Insulator (SOI) 0.75 µm Process (Leff = 0.6 µm) · Total Dose Hardness through 1x10 rad (SiO2) · Neutron Hardness through 1x1014 cm-2 · Dynamic and Static Transient Upset Hardness through 1x109 rad (Si)/s · Dose Rate Survivability through 1x1011 rad(Si)/s · Soft Error Rate of <1x10-10 Upsets/bit-day in Geosynchronous Orbit · No Latchup
6
OTHER · Listed on SMD #5962-96840 · Read/Write Cycle Times 20 ns (Typical) 30 ns (-55 to 125°C) · Asynchronous Operation · CMOS Compatible I/O · Single 5 V ± 10% Power Supply · Low Operating Power · 200-Lead Quad Flat Pack (2.1 in. x 2.1 in.)
GENERAL DESCRIPTION
A major emphasis in Honeywell's packaging program is the use of multichip modules (MCMs). Use of multichip modules will result in higher density packaging of integrated circuits (ICs) and components, lower weight and volume associated with size reduction, higher performance due to a decrease in interconnect length, and additional improvement with new material systems. Honeywell has had a leading role in the development and application of space qualified multichip modules for the last 14 years. In conjunction with the basic technology, we have also developed the necessary tools and methodology for the design of MCMs, Known Good Die (KGD) testing, materials/processes for assembly of MCMs, and test capability for MIL STD and QML screening. The 5M Memory Module is organized into two separate 64K x 40 memory banks. Each memory bank contains two 32K x 40 blocks, using five SRAMs each. The two banks of memory are connected to different busses, making them logically and physically separate within each bank. Only one block is enabled and consuming power at any given time. The die are packaged in a 200-pin 2.1" x 2.1" cofired substrate ceramic flat package.
HX84050
FUNCTIONAL DIAGRAMS
64K x 40 Memory Bank I
I_ Address(14:0) I_ NOE I_ NWE I_ CE0 I_ NCS0 32Kx8 Die D_ NOE
64K x 40 Memory Bank D
D_ Address(14:0)
}
D_ NWE I_ DATA(39:0) D_ CE0 D_ NCS0
32Kx8 Die
}
D_ DATA(39:0)
32K x 40 Memory Block 0
32K x 40 Memory Block 0
32Kx8 Die I_ CE1 I_ NCS1 D_ CE1 D_ NCS1
32Kx8 Die
32K x 40 Memory Block 1
32K x 40 Memory Block 1
Figure 1. 2 x 64K x 40 (Top Level Diagram)
BANK I, BLOCK 0
ADDRESS (14 : 0) DATA (39 : 0)
U1 32Kx8 Memory
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
U2 32Kx8 Memory
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
U3 32Kx8 Memory
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
U4 32Kx8 Memory
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
U5 32Kx8 Memory
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
CE NCS NW E NOE
CE NCS NW E NOE
CE NCS NW E NOE
CE NCS NW E NOE
CE NCS NW E NOE
I_ CE0 I_ NCS0 I_ NWE I_ NOE
Figure 2. 32K x 40 Memory Block Functional Diagram
A:3-7,12,14-16
9
Row Decoder
· · ·
32,768 x 8 Memory Array
· · ·
CE NCS
Column Decoder Data Input/Output NWE
WE · CS · CE
8 8 DQ:0-7
NOE
NWE · CS · CE · OE (0 = high Z)
Signal
1 = enabled # Signal
A:0-2, 8-11, 13
8
All controls must be enabled for a signal to pass. (#: number of buffers, default = 1)
Figure 3. 32K x 8 SRAM Functional Diagram 2
HX84050
SIGNAL DEFINITIONS
Signal definitions for an individual SRAM within the five chip 32K x 40 memory block are shown below. A: 0 - 14 Address input pins (A) which select a particular eight bit word within the memory array. A: 0-3 (Column Select) A: 4-11 (Row Select) A: 12-14 (Block Select) DQ: 0 - 7 Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write operation. Negative chip select, when at a low level, allows normal read or write operation. When at a high level it defaults the SRAM to a pre-charge condition and holds the data output drivers in a high impedance state. All input signals except NCS and CE are disabled. The dynamic and DC IDD chip current contribution from all other input circuits caused by input pins transitioning and/or at VDD or VSS is eliminated. If the NCS signal is not used it must be connected to VSS. Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level it allows normal read operation. Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NWE and CE. If the NOE signal is not used it must be connected to VSS. Chip enable, when at a high level, allows normal operation. When at a low level it forces the array to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except CE and NCS. The dynamic and DC IDD chip current contribution from all other input circuits caused by input pins transitioning and/or not at VDD or VSS levels is eliminated. If the CE signal is not used it must be connected to VDD.
NCS
NWE
NOE
CE
TRUTH TABLE
CE H H X L NCS L L H X NWE H L XX XX NOE L X XX XX MODE Read Write Deselected Disabled DQ Data Out Data In High Z High Z
Notes: X: VI=VIH or VIL XX: VSSVIVDD NOE=H: High Z output state maintained for NCS=X, CE=X, NWE=X
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