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Details, datasheet, quote on part number:GM71CS16403CT/CLT-7
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Datasheet text preview:
GM71C(S)16403C/CL
4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM
Description
The GM71C(S)16403C/CL is the new generation dynamic RAM organized 4,194,304 w o r d s x 4 bit. GM71C(S)16403C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)16403C/CL offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71C(S)16403C/CL to be packaged in a standard 300 mil 24(26) pin SOJ, and a standard 300 mil 24(26) pin plastic TSOP II. The package size provides high system bit d e n s i t i e s and is compatible with widely a v a i l a b l e automated testing and insertion equipment. System oriented features include single power supply 5V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.
Features
* 4,194,304 Words x 4 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (5V+/-10%) * Fast Access Time & Cycle Time
(Unit: ns)
tRAC tCAC tRC
GM71C(S)16403C/CL-5 GM71C(S)16403C/CL-6 GM71C(S)16403C/CL-7 50 60 70 13 15 18 84 104 124
tHPC
20 25 30
Pin Configuration 24(26) SOJ
VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 26 25 24 23 22 21
* Low Power Active : 605/550/495mW (MAX) Standby : 11mW (CMOS level : MAX) : 0.83mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 4096 Refresh Cycles/64ms * 4096 Refresh Cycles/128ms (L-version) * Battery backup operation (L-version) * Test function : 16bit parallel test mode
24(26) TSOP II
VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 26 25 24 23 22 21
VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS
8 9 10 11 12 13
19 18 17 16 15 14
8 9 10 11 12 13
19 18 17 16 15 14
(Top View)
Rev 0.1 / Apr'01
GM71C(S)16403C/CL
Pin Description
Pin
A0-A11 A0-A11 I/O1-I/O4 RAS CAS
Function
Address Inputs Refresh Address Inputs Data Input/Data Output Row Address Strobe Column Address Strobe
Pin
WE OE VCC VSS NC
Function
Read/Write Enable Output Enable Power (+5V) Ground No Connection
Ordering Information
Type No.
GM71C(S)16403CJ/CLJ-5 GM71C(S)16403CJ/CLJ-6 GM71C(S)16403CJ/CLJ-7 GM71C(S)16403CT/CLT-5 GM71C(S)16403CT/CLT-6 GM71C(S)16403CT/CLT-7
Access Time
50ns 60ns 70ns 50ns 60ns 70ns
Package
300 Mil 24(26) Pin Plastic SOJ 300 Mil 24(26) Pin Plastic TSOP II
Absolute Maximum Ratings
Symbol TA TSTG VIN/OUT VCC IO U T PT Parameter
Ambient Temperature under Bias Storage Temperature Voltage on any Pin Relative to VSS Supply Voltage Relative to VSS Short Circuit Output Current Power Dissipation
Rating
0 ~ 70 -55 ~ 125 -1.0 ~ 7.0 -1.0 ~ 7.0 50 1.0
Unit
C C V V mA W
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol VCC VIH VIL Parameter
Supply Voltage Input High Voltage Input Low Voltage
Min
4.5 2.4 -1.0
Typ
5.0 -
Max
5.5 6.5 0.8
Unit
V V V
Note: All voltage referred to Vss.
Rev 0.1 / Apr'01
GM71C(S)16403C/CL
DC Electrical Characteristics (VCC = 5V+/-10%, Vss = 0V, TA = 0 ~ 70C)
Symbol VOH VOL IC C 1 Parameter
Output Level Output "H" Level Voltage (IOUT = -2mA) Output Level Output "L" Level Voltage (IOUT = 2mA) Operating Current Average Power Supply Operating Current (RAS, CAS Cycling: tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) EDO Page Mode Current Average Power Supply Current EDO Page Mode (tHPC = tHPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >= VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) 50ns 60ns 70ns ICC7 Battery Backup Operating Current(Standby with CBR Refresh) (CBR refresh, tRC = 31.3us, tRAS <= 0.3us, DOUT = High-Z, CMOS interface) Standby Current RAS = VIH CAS = VIL DOUT = Enable Input Leakage Current Any Input (0V<=VIN<= 6V) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 6V) 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns
Min
2.0 0 -
Max
VCC 0.4 90 80 70 2 90 80 70 80 70 65 1 150 90 80 70 350
Unit
V V
Note
mA
1, 2
IC C 2
mA
IC C 3
mA
2
IC C 4
mA
1, 3
ICC5
mA uA 5
ICC6
mA
-
uA
4, 5
ICC8
-
5
mA
1
IL(I) IL(O)
-10 -10
10 10
uA uA
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (<=0.2) while RAS = L (<=0.2). 5. L-version.
Rev 0.1 / Apr'01
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