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Details, datasheet, quote on part number:GM71VS16163CT/CLT-6
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Datasheet text preview:
1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM
GM71V16163C GM71VS16163CL
Description
The GM71V(S)16163C/CL is the new generation d y n a m i c RAM organized 1,048,576 x 16 bit. GM71V(S)16163C/CL has realized higher density, higher performance and various functions by utilizing a d v a n c e d CMOS process technology. The G M 7 1 V ( S ) 1 6 1 6 3 C / C L offers Extended Data o u t ( E D O ) Mode as a high speed access mode. Multplexed address inputs permit the GM71V(S)16163C/CL to be packaged in standard 4 0 0 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with w i d e l y available automated testing and insertion equipment.
Features
* 1,048,576 Words x 16 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (3.3V+/-0.3V) * Fast Access Time & Cycle Time (Unit: ns)
tRAC tCAC tRC
GM71V(S)16163C/CL-5 GM71V(S)16163C/CL-6 GM71V(S)16163C/CL-7 GM71V(S)16163C/CL-8 50 60 70 80 13 15 18 20 84 104 124 144
tHPC
20 25 30 35
Pin Configuration 42 SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
* Low Power Active : 396/360/324/288mW (MAX) Standby : 7.2mW (MAX) 0.83mW (L-series : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 4096 Refresh Cycles/64ms * 4096 Refresh Cycles/128ms (L-series) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-series) * 2 CAS byte Control
44(50) TSOP II
VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC
15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC
1 2 3 4 5 6 7 8 9 10 11
50 49 48 47 46 45 44 43 42 41 40
VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC
(Top View)
NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
Rev 0.1 / Apr'01
GM71V16163C GM71VS16163CL
Pin Description
Pin
A0-A11 A0-A11 I/O0-I/O15 RAS CAS
Function
Address Inputs Refresh Address Inputs Data-In/Out Row Address Strobe Column Address Strobe
Pin
WE OE VCC VSS NC
Function
Write Enable Output Enable Power (+3.3V) Ground No Connection
Ordering Information
Type No.
GM71V(S)16163CJ/CLJ -5 GM71V(S)16163CJ/CLJ -6 GM71V(S)16163CJ/CLJ -7 GM71V(S)16163CJ/CLJ -8 GM71V(S)16163CT/CLT -5 GM71V(S)16163CT/CLT -6 GM71V(S)16163CT/CLT -7 GM71V(S)16163CT/CLT -8
Access Time
50ns 60ns 70ns 80ns 50ns 60ns 70ns 80ns
Package
400 Mil 42 Pin Plastic SOJ 400 Mil 44(50) Pin Plastic TSOP II (Normal Type)
Absolute Maximum Ratings*
Symbol TA TSTG VT VCC IO U T PT Parameter
Ambient Temperature under Bias Storage Temperature Voltage on any Pin Relative to VSS Supply Voltage Relative to VSS Short Circuit Output Current Power Dissipation
Rating
0 ~ 70 -55 ~ 125 -0.5 ~ Vcc+0.5 (<=4.6V(MAX)) -0.5 ~ 4.6 50 1.0
Unit
C C V V mA W
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol VCC VIH VIL Parameter
Supply Voltage Input High Voltage Input Low Voltage
Min
3.0 2.0 -0.3
Typ
3.3 -
Max
3.6 VCC + 0.3 0.8
Unit
V V V
*Note: All voltage referred to Vss.
Rev 0.1 / Apr'01
GM71V16163C GM71VS16163CL
Truth Table RAS
H L L L L L L L L L L L L H to L H to L H to L L L
LCAS
D L H L L H L L H L L H L H L L H L
UCAS
D H L L H L L H L L H L L L H L H L
WE
D H H H L L L L L L H to L H to L H to L D D D D H
OE
D L L L D D D H H H L to H L to H L to H D D D D H
Output
Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Open
Operation
Standby Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Word Word Word Word CBR Refresh or Self Refresh (L-series) LAS-only Refresh cycle Read-modify -write cycle Delayed Write cycle Early write cycle Read cycle
Notes
1,3
1,3
1,2,3
1,2,3
1,3
1,3
1,3 1,3
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low(active) D: H or L 2. tWCS >= 0ns Early write cycle tWCS < 0ns Delayed write cycle 3. Mode is determined by the OR fuction of the UCAS and LCAS. (Mode is set by earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edgs.) However write OPERATION and output HIZ control are done independently by each UACS,LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr'01
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