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Details, datasheet, quote on part number:HY5DU281622T-L
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Datasheet text preview:
HY5DU281622
4 Banks x 2M x 16Bit Double Data Rate SDRAM
PRELIMINARY
DESCRIPTION
The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is organized as 4 banks of 2,097,152x16. HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 ), the number of consecutive read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM.
FEATURES
· · · · · 2.5V VDD and VDDQ power suppliy All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock operations(CLK & CLK) with 100MHz/125MHz/133MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ) and Write masks(LDM/UDM) latched on both rising and falling edges of the Data Stobe Data outputs on LDQS/UDQS edges when read (edged DQ) Data inputs on LDQS/UDQS centers when write (centered DQ) · · · · · · · · · · Delay Locked Loop(DLL) installed with DLL reset mode Write mask byte controlled by LDM and UDM Bytewide data strobes by LDQS and UDQS Programmable CAS Latency 2 and 2.5 supported Write Operations with 1 Clock Write Latency /QFC & Half Strength Driver controlled by EMRS Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 4096 refresh cycles / 64ms
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ORDERING INFORMATION
Part No.
HY5DU281622(L)T-K HY5DU281622(L)T-H HY5DU281622(L)T-L
* (L) Low Power Part
Power Suppy
Clock Frequency
143MHz (*PC266A)
Organization
Interface
Package
VDD=2.5V VDDQ=2.5V
133MHz (*PC266B) 125MHz (*PC200)
4Banks x 2Mbit x 16
SSTL_2
400mil 66pin TSOP II
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Mar.00
HY5DU281622
PIN CONFIGURATION
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD /QFC, NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 TOP VIEW 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
400mil X 875mil 66 Pin TSOP-II 0.65mm Pin Pitch
PIN DESCRIPTION
PIN CLK, CLK CKE CS BA0, BA1 A0 ~ A11 RAS, CAS, WE LDM, UDM LDQS, UDQS DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ VREF /QFC (optional) NC PIN NAME Differential Clock Input Clock Enable Chip Select Bank Select Address Address Row Address Strobe, Column Address Strobe, Write Enable Write Mask Data Input/Output Strobe Data Input/Output Power Supply/Ground Data Output Power/Ground Reference Voltage DQ FET Switch Control No Connection DESCRIPTION The system clock input. All of the inputs are latched on the rising edges of the clock except DQi, LDQS/UDQS and LDM/UDM that are sampled on the both. Controls internal clock signal and when deactivated, the DDR SDRAM will be one of the states among power down, suspend or self refresh. Enables or disables all inputs except CLK/CLK, CKE, L/UDQS and L/UDM. Selects bank to be activated during either RAS or CAS activity. Selects bank to be read/written during either RAS or CAS activity. Row Address : A0 ~ A11, Column Address : A0 ~ A8, AP Flag : A10 RAS, CAS and WE define the operations. Refer function truth table for details. Masks input data in write mode. Active on the both edges for Data Input and Output. Multiplexed data input / output pin. Power supply for internal circuits and input buffers. Power supply for output buffers for Noise immunity. Reference voltage for inputs for SSTL interface. Controls FET Switches on DQs used for reduction of Impedance. No connection.
Rev. 1.2 / Mar.00
2
HY5DU281622
FUNCTIONAL BLOCK DIAGRAM
4banks x 2Mbit x 16 I/O Double data rate Synchronous DRAM
W r i t e Data Register 2-bit Prefetch Unit 32 CLK /CLK CKE /CS /RAS /CAS /WE DM Bank Control Command Decoder 2M x 1 6 / B a n k 0 Sense AMP 2M x 1 6 / B a n k 1 2Mx16/Bank2 2Mx16/Bank3 Mode Register Row Decoder 32
16
Input Buffer
DS
2-bit Prefetch Unit
Output Buffer
16
DQ[0:15]
Column Decoder
DQS ADD Address Buffer C o l u m n Address Counter CLK_DLL DS CLK DLL Block D a t a Strobe Transmitter D a t a Strobe Receiver
Mode Register
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time TA T STG VIN, VOUT V DD V DDQ I OS PD T SOLDER Symbol 0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 1 260 10 Rating
o o
Unit C C
V V V mA W
o
C Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
Rev. 1.2 / Mar.00
3
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