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Part: HY5DU281622T
Category:
Memory
-> DRAM
-> DDR SDRAM
-> 128 Mb
Description: 128M(8Mx16) DDR Sdram
Company: Hynix Semiconductor
Datasheet: Download HY5DU281622T datasheet File size : 908 kB
Request For quote: Find where to buy HY5DU281622T
Datasheet text preview:
HY5DU28422T HY5DU28822T HY5DU281622T
2nd 128M DDR SDRAM
HY5DU28422T HY5DU28822T HY5DU281622T
Revision 1.3 April 2001
Rev. 1.3 / Apr. 2001
This document is a general product description and is subject to change without notice.
128Mb (x4, x8, x16) Double Data Rate SDRAM
HY5DU28422T HY5DU28822T HY5DU281622T
CONTENTS
1. 128M DDR SDRAM Brief Information --------------------------------------------------------------------- 3 1.1 Description 1.2 Feature 1.3 Ordering Information 2. Pin 2.1 2.2 2.3 & PKG Information --------------------------------------------------------------------------------------- 4 Pin Configuration Pin Description PKG Physical Dimension
3. Functional Block Diagram ----------------------------------------------------------------------------------- 7 4. Command Truth Table ---------------------------------------------------------------------------------------- 8 4.1 Simplified Command Truth Table 4.2 Write Mask Truth Table 4.3 Operation Command Truth Table 4.4 CKE Function Truth Table 5. Function Description ---------------------------------------------------------------------------------------- 15 5.1 Simplified State Diagram 5.2 Power up Sequence and Device Initialization 5.3 MRS / EMRS Definition 5.4 Device Operation 6. Absolute Maximum Rating -------------------------------------------------------------------------------- 33 7. DC Operating Condition ------------------------------------------------------------------------------------- 33 8. DC Characteristics -------------------------------------------------------------------------------------------- 34 9. AC Operating Test Condition ------------------------------------------------------------------------------ 35 10. AC Characteristics ------------------------------------------------------------------------------------------ 36 11. Input / Output Capacitance & Output Load Circuit ---------------------------------------------- 38 12. Output Drive Characteristics ---------------------------------------------------------------------------- 39 12.1 Full Strength Drive 13. Timing Diagram --------------------------------------------------------------------------------------------- 43
Rev. 1.3 / Apr. 2001
2
128Mb (x4, x8, x16) Double Data Rate SDRAM
DESCRIPTION
HY5DU28422T HY5DU28822T HY5DU281622T
The Hynix HY5DU28422, HY5DU28822 and HY5DU281622 are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURESHynix
· · · · · · · VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe · · · · · · · · All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 2 and 2.5 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported 4096 refresh cycles / 64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full strength driver option controlled by EMRS
· ·
ORDERING INFORMATION
Part No.
HY5DU28422T-X* HY5DU28422LT-X* HY5DU28822T-X* HY5DU28822LT-X* HY5DU281622T-X* HY5DU281622LT-X* Rev. 1.3 / Apr. 2001
OPERATING FREQUENCY
Power
Standard Low Power Standard Low Power Standard Low Power 3
Configuration
32Mx4 32Mx4 16Mx8 16Mx8 8Mx16 8Mx16
Grade
-H -L
CL2
125MHz 100MHz
CL2.5
133MHz 125MHz
Remark**
DDR266B DDR200
* X means speed grade ** JEDEC specification compliant
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