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Details, datasheet, quote on part number:HYM71V8M635HCT6-H
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Datasheet text preview:
8Mx64 bits PC133 SDRAM SO DIMM
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V8M635HC(L)T6 Series
DESCRIPTION
The Hynix HYM71V8M635HC(L)T6 Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of four 8Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V8M635HC(L)T6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The Hynix HYM71V8M635HC(L)T6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
· · · · PC133/PC100MHz support 144pin SDRAM SO DIMM Serial Presence Detect with EEPROM 1.00" (25.40mm) Height PCB with double sided components Single 3.3±0.3V power supply - 1, 2, 4 or 8 or Full page for Sequential Burst · · All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Interleave Burst Data mask function by DQM · Programmable CAS Latency ; 2, 3 Clocks · · · · · · SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HY M71V 8M635HCT 6-K HYM71V8M635HCT6-H HYM71V8M635HCLT6-K HYM71V8M635HCLT6-H 133M Hz 4 Banks 4K Low Power
Cloc k Frequency
Internal Ba nk
Ref.
Power
Norm al
SDRAM Package
Plating
TSOP-II
G old
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3/Dec. 01 2
PC133 SDRAM SO DIMM
HYM71V8M635HC(L)T6 Series
PIN DESCRIPTION
PIN CK0, CK1 CK E0 /S0 BA0, BA1 A0 ~ A11 /RAS, /CAS, /WE DQM0~DQM7 DQ0 ~ DQ63 V CC VSS S CL S DA SA0~2 WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers G ro u n d Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM No connection
Rev. 0.3/Dec. 01
3
PC133 SDRAM SO DIMM
HYM71V8M635HC(L)T6 Series
PIN ASSIGNMENTS
FRONT SIDE PIN NO.
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
BACK SIDE PIN NO.
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
FRONT SIDE PIN NO.
71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133
BACK SIDE PIN NO.
72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
NAM E
VSS DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7 VSS DQM0 DQM1 VCC A0 A1 A2 VSS DQ 8 DQ 9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC
NAM E
VSS DQ32 DQ33 DQ34 DQ35 V CC DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 V CC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ4 3 V CC DQ44 DQ45 DQ46 DQ47 VSS NC NC
NAM E
NC NC VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 V CC A6 A8 VSS A9 A10/AP V CC DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 V CC DQ28 DQ29 DQ30 DQ31 VSS S DA V CC
N AME
NC *CK1 VSS NC NC V CC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 V CC A7 BA0 VSS BA1 A11 V CC DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 V CC DQ60 DQ61 DQ62 DQ63 VSS S CL V CC
Voltage Key
61 63 65 67 69 CK 0 VCC /RAS /WE /S0 62 64 66 68 70 CK E 0 V CC /CAS NC NC
135 137 139 141 143
Note : * CK1 are connected with termination R/C (Refer to the Block Diagram)
Rev. 0.3/Dec. 01
4
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