Details, datasheet, quote on part number: HYM71V8M655ALTU6-P
CategoryMemory => DRAM => SDR SDRAM => Modules => 64 MB => ->SO DIMM
Title->SO DIMM
CompanyHynix Semiconductor
DatasheetDownload HYM71V8M655ALTU6-P datasheet


Features, Applications
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh

The Hynix HYM71V8M655ATU6 Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of four 8Mx16bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V8M655ATU6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The Hynix HYM71V8M655ATU6 Series are fully synchronous operation referenced to the positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.


PC100MHz support 144pin SDRAM Micro SO DIMM Serial Presence Detect with EEPROM 1.18" (30.00mm) Height PCB with double sided components Single 3.30.3V power supply All device pins are compatible with LVTTL interface or 8 for Interleave Burst Data mask function by DQM Programmable CAS Latency 2, 3 Clocks SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type 8 or Full page for Sequential Burst

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 01 2

PIN ~ A11 /RAS, /CAS, /WE ~ DQ63 VCC VSS SCL SDA NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address ~ RA11, Column Address ~ CA8 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output No connection

Note * CK1 are connected with termination R/C (Refer to the Block Diagram)


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