Details, datasheet, quote on part number: HYM71V8M655BLT6
PartHYM71V8M655BLT6
CategoryMemory => DRAM => SDR SDRAM => Modules => 64 MB => ->SO DIMM
Title->SO DIMM
Description
CompanyHynix Semiconductor
DatasheetDownload HYM71V8M655BLT6 datasheet
  

 

Features, Applications
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh

The Hynix HYM71V8M655B(L)T6 Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of four 8Mx16bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V8M655B(L)T6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The Hynix HYM71V8M655B(L)T6 Series are fully synchronous operation referenced to the positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

FEATURES

PC100MHz support 144pin SDRAM SO DIMM Serial Presence Detect with EEPROM 1.00" (25.40mm) Height PCB with double sided components Single 3.30.3V power supply All device pins are compatible with LVTTL interface or 8 for Interleave Burst Data mask function by DQM Programmable CAS Latency 2, 3 Clocks SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type 8 or Full page for Sequential Burst

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 01 2

PIN ~ A11 /RAS, /CAS, /WE ~ DQ63 VCC VSS SCL SDA WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address ~ RA11, Column Address ~ CA8 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM No connection

Note * CK1 are connected with termination R/C (Refer to the Block Diagram)

 

Related products with the same datasheet
HYM71V8M655BLT6-8
HYM71V8M655BLT6-P
HYM71V8M655BLT6-S
HYM71V8M655BT6-8
HYM71V8M655BT6-P
HYM71V8M655BT6-S
Some Part number from the same manufacture Hynix Semiconductor
HYM71V8M655BLT6-8
HYM71V8M655BT6
HYM71V8M655BT6-8
HYM71V8M655HCLT6 8Mx64 Bits PC100 Sdram so Dimm Based on 8Mx16 Sdram With Lvttl, 4 Banks & 4K Refresh
HYM71V8M655HCLT6-8
HYM71V8M655HCLT6-P 8Mx64 Bits PC100 Sdram so Dimm Based on 8Mx16 Sdram With Lvttl, 4 Banks & 4K Refresh
HYM71V8M655HCLT6-P
HYM71V8M655HCLTU6 8Mx64 Bits PC100 Sdram so Dimm Based on 8Mx16 Sdram With Lvttl, 4 Banks & 4K Refresh
HYM71V8M655HCLTU8-P
HYM71V8M655HCT6
HYM71V8M655HCTU6 8Mx64 Bits PC100 Sdram so Dimm Based on 8Mx16 Sdram With Lvttl, 4 Banks & 4K Refresh
HYM71V8M655HCTU6-P
HYM71V8M755HCFU6
HYM71V8M755HCLFU6
HYM71V8M755HCLFU6-8
HYM72V12C736BLS4 128Mx72 Bits PC133 Sdram Registered Dimm With Pll, Based on 64Mx4 Sdram With Lvttl, 4 Banks & 8K Refresh
HYM72V12C736BLS4-H
HYM72V12C736K4 128Mx72 Bits PC133 Sdram Registered Dimm With Pll, Based on 64Mx4 Sdram With Lvttl, 4 Banks & 8K Refresh
HYM72V12C756BLS4 128Mx72 Bits PC100 Sdram Registered Dimm With Pll, Based on 64Mx4 Sdram With Lvttl, 4 Banks & 8K Refresh
HYM72V12C756BLS4-P
HYM72V12C756K4 128Mx72 Bits PC100 Sdram Registered Dimm With Pll, Based on 64Mx4 Sdram With Lvttl, 4 Banks & 8K Refresh
Same catergory

AAM29LV400BB120EC : 4 Megabit ( 512 K X 8-bit/256 K X 16-bit ) CMOS 3.0 Volt-only Boot Sector Flash Memory.

AT49BV080 : 8-megabit 1m X 8 Single 2.7-volt Battery-voltage Flash Memory. Single Supply for Read and Write: to 3.6V (BV), to 3.6V (LV) Fast Read Access Time 120 ns Internal Program Control and Timer 16K bytes Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Byte-By-Byte Programming - 30 s/Byte Typical Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation 25 mA Active Current 50 A CMOS.

HT27LC4096 : HT27LC4096 CMOS 256Kx16-Bit OTP EPROM. Operating voltage: +3.3V Programming voltage VCC=6.0V0.2V 256K16-bits organization Fast read access time: 90ns Fast programming algorithm Programming time 75ms typ. Two line controls (OE and CE) Standard product identification code Commercial temperature range +70C) 40-pin plastic DIP package High-reliability CMOS technology Latch-up immunity to 100mA.

M372F0883BT0 : Buffered DIMM. = M372F0883BT0 8Mx72 DRAM Dimm With Ecc Using 8Mx8,4K&8KRefresh,3.3V ;; Density(MB) = 64 ;; Organization = 8Mx72 ;; Mode = Edo ;; Refresh = 8K/64ms ;; Speed(ns) = 50,60 ;; #of Pin = 168 ;; Component Composition = (8Mx8)x9+Drive ICx2 ;; Production Status = Eol ;; Comments = Buffered.

MT8VDDT3264HG-40B__ : 200-Pin DDR Sdram Sodimms, PC3200, (x64). 200-pin, small-outline, dual in-line memory module (SODIMM) Fast data transfer rates: PC3200 Utilizes 400 MT/s DDR SDRAM components: 256MB (32 Meg 512MB (64 Meg x 64) VDD = VDDQ = +2.6V VDDSPD +3.6V 2.6V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs Internal,.

UD61464 : Asynchronous->5V FPM. 64kx4 DRAM.

WED9LAPC2B16P8BC : Application Specific. Organization = 4Mx32/2Mx8 ;; Speed MHZ = 100 ;; Volt = 3.3 ;; Package = 153 Pbga ;; Temp = C,i ;;.

X28C010 : 1 M Bit CMOS EePROM. Access Time: 120ns Simple Byte and Page Write --Single 5V Supply --No External High Voltages or VPP Control Circuits --Self-Timed No Erase Before Write No Complex Programming Algorithms No Overerase Problem Low Power CMOS: --Active: 50mA --Standby: 500A Software Data Protection --Protects Data Against System Level Inadvertant Writes High Speed Page.

CY7C1081DV33-12BAXI : 4M X 16 STANDARD SRAM, 12 ns, PBGA48. s: Memory Category: SRAM Chip ; Density: 67109 kbits ; Number of Words: 4000 k ; Bits per Word: 16 bits ; Package Type: 8 X 9.50 MM, 1.40 MM HEIGHT, LEAD FREE, MO-205, FBGA-48 ; Pins: 48 ; Logic Family: CMOS ; Supply Voltage: 3.3V ; Access Time: 12 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F).

DS1207-001 : SPECIALTY MEMORY CIRCUIT, SSS. s: Operating Temperature: 0 to 70 C (32 to 158 F).

IDT70V06L15GG : 16K X 8 DUAL-PORT SRAM, 15 ns, CPGA68. s: Memory Category: SRAM Chip ; Density: 131 kbits ; Number of Words: 16 k ; Bits per Word: 8 bits ; Package Type: CERAMIC, PGA-68 ; Pins: 68 ; Logic Family: CMOS ; Supply Voltage: 3.3V ; Access Time: 15 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).

IDT72210L10TC : 512 X 8 OTHER FIFO, 6.5 ns, CDIP28. s: Memory Category: FIFO ; Density: 4 kbits ; Number of Words: 512 k ; Bits per Word: 8 bits ; Package Type: DIP, 0.300 INCH, THIN, SIDE BRAZED, DIP-28 ; Pins: 28 ; Logic Family: CMOS ; Supply Voltage: 5V ; Access Time: 6.5 ns ; Cycle Time: 10 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).

TC58NVG0S3EBAI4 : 128M X 8 EEPROM 3V, PBGA63. s: Density: 1024459 kbits ; Number of Words: 128000 k ; Bits per Word: 8 bits ; Bus Type: Serial ; Production Status: Full Production ; Logic Family: CMOS ; Supply Voltage: 3V ; Package Type: 9 X 11 MM, 0.80 MM PITCH, PLASTIC, TFBGA-63 ; Pins: 63 ; Operating Range: Industrial ; Operating Temperature: -40 to 85 C (-40 to 185 F).

W68C254A-12G : 32K X 8 STANDARD SRAM, 120 ns, PDSO28. s: Memory Category: SRAM Chip ; Density: 262 kbits ; Number of Words: 32 k ; Bits per Word: 8 bits ; Package Type: SOIC, 0.350 INCH, SOIC-28 ; Pins: 28 ; Logic Family: CMOS ; Supply Voltage: 3V ; Access Time: 120 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).

WEDPS512K32-25BC : 512K X 32 MULTI DEVICE SRAM MODULE, 25 ns, PBGA143. s: Memory Category: SRAM Chip ; Density: 16777 kbits ; Number of Words: 512 k ; Bits per Word: 32 bits ; Package Type: BGA, 16 X 18 MM, PLASTIC, BGA-143 ; Pins: 143 ; Logic Family: CMOS ; Supply Voltage: 5V ; Access Time: 25 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).

 
0-C     D-L     M-R     S-Z