Details, datasheet, quote on part number: HYM72V12C756K4
PartHYM72V12C756K4
CategoryMemory => DRAM => SDR SDRAM => Modules => 256 MB
Description128Mx72 Bits PC100 Sdram Registered Dimm With Pll, Based on 64Mx4 Sdram With Lvttl, 4 Banks & 8K Refresh
CompanyHynix Semiconductor
DatasheetDownload HYM72V12C756K4 datasheet
  

 

Features, Applications
with PLL, based on 64Mx4 SDRAM with LVTTL, 4 banks & 8K Refresh
DESCRIPTION

The HYM72V12C756K4 Series are 128Mx72bits ECC Synchronous DRAM Modules. The modules are composed of thirty six 64Mx4bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II stack package, one 2Kbit EEPROM in 8pin TSSOP package a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The HYM72V12C756K4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 1Gbytes memory. The HYM72V12C756K4 Series are fully synchronous operation referenced to the positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

168pin SDRAM Registered DIMM Serial Presence Detect with EEPROM 1.7" (43.18mm) Height PCB with double sided components Single 3.30.3V power supply

SDRAM internal banks : four banks Module bank : two physical banks Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type 8 or Full page for Sequential Burst

All device pins are compatible with LVTTL interface or 8 for Interleave Burst Data mask function by DQM Programmable CAS Latency 2, 3 Clocks

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/Dec.2002

PIN ~ A12 /RAS, /CAS, /WE REGE ~ DQ63 VCC VSS SCL SDA ID1~3 NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Row Address Strobe, Column Address Strobe, Write Enable Register Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD Identification Detect No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address ~ RA12, Column Address CA9, CA11 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Register Enable pin which permits the DIMM to operateion in Buffered Mode when REGE input is Low, in Registered Mode when REGE input is High Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM Commend Interval, Read Precharge Timing, Power Detect No connection


 

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