Details, datasheet, quote on part number: HYM72V16M656BT6-S
CategoryMemory => DRAM => SDR SDRAM => Modules => 128 MB => ->SO DIMM
Title->SO DIMM
CompanyHynix Semiconductor
DatasheetDownload HYM72V16M656BT6-S datasheet


Features, Applications
based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh

The HYM72V16M656B(L)T6 -Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four 16Mx16 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM a 144-pin Zig Zag Dual pin glass-epoxy printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the module. The HYM72V16M656B(L)T6 -Series are gold plated socket type Dual In-line Memory Modules suitable for easy interchange and addition of 128M bytes memory. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.


PC100 support 144pin SDRAM SO DIMM Serial Presence Detect with EEPROM 1.00" (25.40mm) Height PCB with double sided components Single 3.30.3V power supply 8 or Full page for Sequential Burst All device pins are compatible with LVTTL interface or 8 for Interleave Burst Data mask function by DQM Programmable CAS Latency 2, 3 Clocks SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 02 1

PIN ~ A12 /RAS, /CAS, /WE ~ DQ63 VCC VSS SCL SDA WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address ~ RA12, Column Address ~ CA8 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM No connection

Note * CK1 are connected with termination R/C (Refer to the Block Diagram)


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