|Category||Memory => DRAM => SDR SDRAM => Modules => 256 MB|
|Description||16Mx64 Bits PC100 Sdram so Dimm Based on 16Mx16 Sdram With Lvttl, 4 Banks & 8K Refresh|
|Datasheet||Download HYM72V16M656HT6 datasheet
|based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh
The HYM72V16M656H(L)T6 -Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four 16Mx16 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM a 144-pin Zig Zag Dual pin glass-epoxy printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the module. The HYM72V16M656H(L)T6 -Series are gold plated socket type Dual In-line Memory Modules suitable for easy interchange and addition of 128M bytes memory. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.FEATURES
PC100 support 144pin SDRAM SO DIMM Serial Presence Detect with EEPROM 1.0" (25.4mm) Height PCB with double sided components Single 3.3±0.3V power supply 8 or Full page for Sequential Burst All device pins are compatible with LVTTL interface or 8 for Interleave Burst Data mask function by DQM Programmable CAS Latency 2, 3 Clocks SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Nov. 01
PIN ~ A12 /RAS, /CAS, /WE ~ DQ63 VCC VSS SCL SDA WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address ~ RA12, Column Address ~ CA8 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM No connectionNote * CK1 are connected with termination R/C (Refer to the Block Diagram)
|Some Part number from the same manufacture Hynix Semiconductor|
|HYM72V16M656HT6-S 16Mx64 Bits PC100 Sdram so Dimm Based on 16Mx16 Sdram With Lvttl, 4 Banks & 8K Refresh|
|HYM72V32636BLT8 32Mx64bits PC133 Sdram Unbuffered Dimm Based on 32Mx8 Sdram With Lvttl, 4 Banks & 8K Refresh|
|HYM72V32636HLT8 32Mx64bits PC133 Sdram Unbuffered Dimm Based on 32Mx8 Sdram With Lvttl, 4 Banks & 8K Refresh|
|HYM72V32636T8 32Mx64bits PC133 Sdram Unbuffered Dimm Based on 32Mx8 Sdram With Lvttl, 4 Banks & 8K Refresh|
|HYM72V32656BLT8 32Mx64bits PC100 Sdram Unbuffered Dimm Based on 32Mx8 Sdram With Lvttl, 4 Banks & 8K Refresh|
|HYM72V32656HLT8 32Mx64bits PC100 Sdram Unbuffered Dimm Based on 32Mx8 Sdram With Lvttl, 4 Banks & 8K Refresh|
|HYM72V32656T8 32Mx64bits PC100 Sdram Unbuffered Dimm Based on 32Mx8 Sdram With Lvttl, 4 Banks & 8K Refresh|
|HYM72V32736BLT8 32Mx72 Bits PC133 Sdram Unbuffered Dimm Based on 32Mx8 Sdram With Lvttl, 4 Banks & 8K Refresh|
AAM29LV160DB-120EC : 16 Megabit ( 2 M X 8-bit/1 M X 16-bit ) CMOS 3.0 Volt-only Boot Sector Flash Memory.
AT45DB081B : . Single - 3.6V Supply Serial Peripheral Interface (SPI) Compatible 20 MHz Max Clock Frequency Page Program Operation Single Cycle Reprogram (Erase and Program) 4096 Pages (264 Bytes/Page) Main Memory Supports Page and Block Erase Operations Two 264-byte SRAM Data Buffers Allows Receiving of Data while Reprogramming of Nonvolatile Memory Continuous.
FFD35US-1024-T-PXX : Fast Flash Disks. Fast Flash Disk 3.5" Ultra Wide Scsi. High-Performance, High-Density Solid-State Flash Disk Technology Overview M-Systems' Fast Flash Disk (FFD) 3.5" Ultra-Wide SCSI is a state-of-the-art solid-state disk based on NAND flash technology, with no moving parts. FFD 3.5" Ultra-Wide SCSI implements M-Systems' TrueFFS® technology to provide full disk emulation, enhanced endurance with dynamic.
GM71V17400C : . The GM71V(S)17400C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71V(S)17400C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)17400C/CL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the to be packaged.
HY57V56420T : 4 Banks X 16M X 4Bit Synchronous DRAM. The a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V56420 is organized as 4 banks of 16,777,216x4. The HY57V56420T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising.
HYM71V16M635ALT8 : ->SO DIMM. based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh The Hynix HYM71V16M635AT8 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package a 144pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors.
HYM71V32755ALT8-8 : ->Unbuffered DIMM. based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh The Hynix HYM71V32755AT8 Series are 32Mx72bits ECC Synchronous DRAM Modules. The modules are composed of eighteen 16Mx8bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling.
K4C89363AF : Network DRAM->288M bit. = K4C89363AF 2,097,152-WORDS X 4 Banks X 36-BITS Double Data Rate Network-dram ;; Organization = 8Mx36 ;; Voltage(V) = 2.5 ;; Refresh = 8K/32ms ;; Bank/ Interface = 4B/SSTL_1.8 ;; Speed(MHz) = F6,FB,F5 ;; TRAC(ns) = 20~25 ;; Package = 144FBGA ;; Production Status = Engineering Sample:4Q'2003 ;; Comments = Target Spec.
K7A403600M : SB & SPB. = K7A403600M 128Kx36-Bit Synchronous Pipelined Burst SRAM ;; Organization = 128Kx36 ;; Operating Mode = SPB ;; VDD(V) = 3.3 ;; Access Time-tCD(ns) = 3.5,3.8,4.0,4.0 ;; Speed-tcyc (MHz) = 250,225,200,183,175,167,150,138,117 ;; I/o Voltage(V) = 2.5,3.3 ;; Package = 100TQFP ;; Production Status = Eol ;; Comments = 2E1D.
KT6472SRN3R : ->DIMM. 512 Mega Byte x 72) SDRAM Preliminary Registered 168 Pin DIMM Ultra Low Profile This memory module is a high performance 512 Megabyte Registered synchronous dynamic RAM module organized a 168-pin Dual In-Line Memory Module (DIMM) package. The module utilizes thirty-six (36) 8Mx4X4 SDRAM devices in a TSOP II 400 mil package. A 256 Byte Serial EEPROM.
M368L0914BT0 : = M368L0914BT0 8Mx64 DDR Sdram 184pin Dimm Based on 8Mx16 ;; Density(MB) = 64 ;; Organization = 8Mx64 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 4K/64ms ;; Speed = A2,B0,A0 ;; #of Pin = 184 ;; Power = C,l ;; Component Composition = (8Mx16)x4 ;; Production Status = Eol ;; Comments = 64bit Non-ecc/parity.
MX27L2000 : . 256Kx 8 organization Wide power supply range, DC +12.5V programming voltage Fast access time: 70R/120/150/200/250 ns Totally static operation Completely TTL compatible Operating 3.6V, 5MHz The a 3V only, 2M-bit, One Time Programmable Read Only Memory. It is organized as 256K words by 8 bits per word, operates from a single + 3 volt supply, has a static.
UT62256 : 32k X 8 Bit Low Power CMOS SRAM.
K7P323674C : 1Mx36 Synchronous Pipelined SRAM The K7P323674C is 37,748,736 bit Synchronous Pipeline Mode SRAM. It is organized as 1,048,576 words of 36 bits and is implemented in SAMSUNG's advanced CMOS technology. Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge.
SST88VP1107 : All-in-OneMemory he SST88VP1107 is a reliable, high-performance, single package, managed memory subsystem for code and data storage that is easy to use. Designed for embedded applications including mobile phones and portable consumer electronics, this product provides an all-in-one memory solution through its unique capability to configure its various.
MCM63F737TQ10 : 128K X 36 CACHE SRAM, 10 ns, PQFP100. s: Memory Category: SRAM Chip ; Density: 4719 kbits ; Number of Words: 128 k ; Bits per Word: 36 bits ; Package Type: TQFP, TQFP-100 ; Pins: 100 ; Supply Voltage: 3.3V ; Access Time: 10 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).
MT41J128M16HA-093:D : 128M X 16 DDR DRAM, PBGA96. s: Memory Category: DRAM Chip ; Density: 2147484 kbits ; Number of Words: 128000 k ; Bits per Word: 16 bits ; Package Type: 9 X 14 MM, LEAD FREE, FBGA-96 ; Pins: 96 ; Logic Family: CMOS ; Supply Voltage: 1.5V ; Operating Temperature: 0 to 85 C (32 to 185 F).
70V05L35GG : 8K X 8 DUAL-PORT SRAM, 35 ns, CPGA68. s: Memory Category: SRAM Chip ; Density: 66 kbits ; Number of Words: 8 k ; Bits per Word: 8 bits ; Package Type: 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68 ; Pins: 68 ; Logic Family: CMOS ; Supply Voltage: 3.3V ; Access Time: 35 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).