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Details, datasheet, quote on part number:HYM72V64C736T4-HP
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Datasheet text preview:
64Mx72 bits PC133 SDRAM Registered DIMM
with PLL, based on 64Mx4 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V64C736(L)T4 Series
DESCRIPTION
The HYM72V64C736(L)T4 Series are 64Mx72bits ECC Synchronous DRAM Modules. The modules are composed of eighteen 64Mx4bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on 512Mbytes memory. The HYM72V64C736(L)T4 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
· · · ·
PC133/PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.70" (43.18mm) Height PCB with double sided components Single 3.3±0.3V power supply
· · · · ·
SDRAM internal banks : four banks Module bank : one physical bank Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4 or 8 or Full page for Sequential Burst
· · ·
All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Interleave Burst Data mask function by DQM · Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY M72V 64C736T 4-HP HYM72V64C736T4-H HYM72V64C736LT4-HP HYM72V64C736LT4-H 133M Hz 4 Banks 8K Low Power
Cloc k Frequency
Internal Ba nk
Ref.
Power
Norm al
SDRAM Package
Plating
TSOP-II
G old
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5/Nov. 01 1
PC133 SDRAM Registered DIMM
HYM72V64C736(L)T4 Series
PIN DESCRIPTION
PIN CK 0~CK3 CK E0 /S0, /S2 BA0, BA1 A0 ~ A12 /RAS, /CAS, /WE REGE DQM0~DQM7 DQ0 ~ DQ63 CB0 ~ CB7 V CC VSS S CL S DA SA0~2 WP NC PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Register Enable Data Input/Output Mask Data Input/Output Check Bit Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9, CA12 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Register Enable pin which permits the DIMM to operateion in Buffered Mode when REGE input is Low, in Registered Mode when REGE input is High Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Check bits for ECC Power supply for internal circuits and input buffers G ro u n d Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect for Serial Presence Detect on DIMM No connection
Rev. 1.5/Nov. 01
2
PC133 SDRAM Registered DIMM
HYM72V64C736(L)T4 Series
PIN ASSIGNMENTS
FRONT SIDE PIN NO.
1 2 3 4 5 6 7 8 9 10
BACK SIDE PIN NO.
85 86 87 88 89 90 91 92 93 94
FRONT SIDE PIN NO.
41 42 43 44 45 46 47 48 49 50 51 52
BACK SIDE PIN NO.
125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
NAM E
VSS DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7
NAM E
VSS DQ32 DQ33 DQ34 DQ35 V CC DQ3 6 DQ37 DQ38 DQ39
NAM E
V CC CK0 VSS NC /S2 DQM2 DQM 3 NC V CC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 V CC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 V CC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP S DA SCL VCC
N AME
*CK1 A12 VSS CKE0 NC DQM6 DQM7 NC V CC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 V CC DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC SA0 SA1 SA2 VCC
Architecture Key
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DQ 8 VSS DQ 9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB 0 CB 1 VSS NC NC VCC /WE DQM0 DQM1 /S0 NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 D Q4 0 VSS DQ41 DQ42 DQ43 DQ44 DQ45 V CC DQ46 DQ47 CB 4 CB 5 VSS NC NC VCC /CAS DQM4 DQM5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 A11 V CC
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Voltage Key
Note : * CK1 ~ CK3 are connected with termination R/C (Rsfer to the block diagram)
Rev. 1.5/Nov. 01
3
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