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Details, datasheet, quote on part number:HYM72V64M636BLF8-K
 
 
Part:HYM72V64M636BLF8-K
Category:Memory => DRAM => SDR SDRAM => Modules => 512 MB => ->SO DIMM
Description:
Company:Hynix Semiconductor
Datasheet:Download HYM72V64M636BLF8-K datasheet   File size : 246 kB
Request For quote:  Find where to buy HYM72V64M636BLF8-K
 



Datasheet text preview:
64Mx64bits PC133 SDRAM SO DIMM
based on 32Mx8 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V64M636B(L)F Series
DESCRIPTION
Preliminary
The HYM72V64M636B(L)F8 is 64Mx64bits Synchronous DRAM Modules. The modules are composed of sixteen 32Mx8bits CMOS Synchronous DRAMs in FBGA package, one 2Kbit EEPROM in 8pin TSOP package on a 144pin glass-epoxy printed circuit board. One 0.1uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The HYM72V64M636B(L)F8 is Small Outline Dual In-line Memory Modules suitable for easy interchange and addition of 512Mbytes memory. The HYM72V64M636B(L)F8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
· · · · · · · · PC133MHz support 144pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.181" Height PCB with double sided components Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface Data mask function by DQM SDRAM internal banks : four banks · · · · · Module bank : two physical bank Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4 or 8 or Full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No. HYM72V64M636BF8-K HYM72V64M636BF8-H HYM72V64M636BLF8-K HYM72V64M636BLF8-H Clock Frequency
133MHz 133MHz 133MHz 133MHz 4 Banks 8K Low Power
Internal Bank
Ref.
Power
Normal
SDRAM Package
Plating
54ball FBGA
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/Apr. 02 1
PC133 SDRAM SO DIMM
HYM72V64M636B(L)F8 Series
PIN DESCRIPTION
PIN CK0, CK1 CKE0 /S0, /S1 BA0, BA1 A0 ~ A12 PIN NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address A ddr ess Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input No Connection DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CK, CKE and DQM Selects bank to be activated during /RAS activity Selects bank to be read/written during /CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 /RAS, /CAS and /WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input No connection
/RAS, /CAS, /WE DQM0~DQM7 DQ0 ~ DQ63 VC C VS S SC L SD A SA0~2 NC
Rev. 0.1/Apr. 02
2
PC133 SDRAM SO DIMM
HYM72V64M636B(L)F8 Series
PIN ASSIGNMENTS
FRONT SIDE PIN NO.
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
BACK SIDE PIN NO.
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
FRONT SIDE PIN NO.
71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133
BACK SIDE PIN NO.
72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
NAME
VSS DQ0 DQ1 DQ2 DQ3 V CC DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ 1 0 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC
NAME
VSS DQ32 DQ33 DQ34 DQ35 V CC DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 V CC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 V CC DQ44 DQ45 DQ46 DQ47 VSS NC NC
NAME
S1 NC VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC A6 A8 VSS A9 A10/AP VCC DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC
NAME
NC CK 1 VSS NC NC V CC DQ 4 8 DQ 4 9 DQ 5 0 DQ 5 1 VSS DQ52 DQ53 DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 V CC DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
Voltage Key
61 63 65 67 69 CK0 VCC /RAS /WE /S0 62 64 66 68 70 CKE0 V CC /CAS NC A 12
135 137 139 141 143
Rev. 0.1/Apr. 02
3