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Details, datasheet, quote on part number:HY51V64400A
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Datasheet text preview:
HY51V64400A,HY51V65400A
16Mx4, Fast Page mode
2nd Generation
DESCRIPTION
This family is a 64M bit dynamic RAM organized 16,777,216 x 4-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode offers high speed of random access memory within the same row. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(50 or 60ns) and r e f r e s h cycle(8K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai's advanced c i r c u i t design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability.
FEATURES
Y Fast page mode operation Y Read-modify-write capability Y Multi-bit parallel test capability Y LVTTL(3.3V) compatible inputs and outputs Y /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability Y Max. Active power dissipation Speed 50 60 Y Refresh cycles Part number HY51V64160A1) HY51V65160A2) Refresh 8K 64ms 4K 128m s Normal L-part 8K refresh 396mW 324mW 4K refresh 504m W 432mW Y JEDEC standard pinout 32-pin plastic SOJ/TSOP-II (400mil) Y Single power supply of 3.3 ± 0.3V Y Early write or output enable controlled write
Y Fast access time and cycle time Speed 50 60 tRAC 50ns 60ns tCAC 13ns 15ns tPC 35ns 40ns
1) Normal read / write, /RAS only refresh : 8K cycles / 64ms /CAS-before-/RAS, Hidden refresh : 4K cycles / 64ms 2) Normal read / write, /RAS only refresh : 4K cycles / 64ms /CAS-before-/RAS, Hidden refresh : 4K cycles / 64ms
ORDERING INFORMATION
Part Name HY51V64400ATC HY51V64400ALTC HY51V64400ASLTC HY51V65400ATC HY51V65400ALTC HY51V65400ASLTC
*SL : Self refresh with low power.
Refresh 8K 8K 8K 4K 4K 4K
Power
Package 32Pin SOJ/TSOP-II
L-part *SL-part
32Pin SOJ/TSOP-II 32Pin SOJ/TSOP-II 32Pin SOJ/TSOP-II
L-part *SL-part
32Pin SOJ/TSOP-II 32Pin SOJ/TSOP-II
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev. 10/Sep.98
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HY51V64400A,HY51V65400A
FUNCTIONAL BLOCK DIAGRAM
DQ0 DQ1 DQ2 DQ3
4
4 Data Output Buffer DQ0~3 OE
Data Input Buffer DQ0~3
WE CAS
4
4
CAS Clock Generator
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 *(A12)
Cloumn Predecoder (11/12)*
(11/12)* Column Decoder
Address Buffer
Refresh Controller
Sense Amp I/O Gate
Refresh Counter Row Decoder Row Predecoder (13/12)* (13/12)* Memory Array 16,777,216 x 4
RAS
RAS Clock Generator Substrate Bias Generator V CC V SS
X32 Parallel Test
*(A12) for 8K refresh part (8K Refresh / 4K Refresh)*
16Mx4,FP DRAM Rev. 10/Sep.98
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HY51V64400A,HY51V65400A
PIN CONFIGURATION (Marking Side)
V CC DQ0 DQ1 N.C N.C N.C N.C WE RAS A0 A1 A2 A3 A4 A5 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
·
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS DQ3 DQ2 N.C N.C N.C CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 V SS
V CC DQ0 DQ1 N.C N.C N.C N.C WE RAS A0 A1 A2 A3 A4 A5 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
·
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS DQ3 DQ2 N.C N.C N.C CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 V SS
32Pin Plastic SOJ (400mil)
32Pin Plastic TSOP-II (400mil)
A12(N.C)* : For 4K refresh product
PIN DESCRIPTION
Pin Name /RAS /CAS /WE /OE A0~A12 A0~A11 DQ0~DQ3 Vcc Vss NC Parameter Row Address Strobe Column Address Strobe Write Enable Output Enable Address Input (8K Refresh Product) Address Input (4K Refresh Product) Data In/Out Power (3.3V) Ground No Connection
16Mx4,FP DRAM Rev.10/Sep.98
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