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Details, datasheet, quote on part number:405EP
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Features
· IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz with 16KB D- and Icaches · PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications · 4 KB on-chip memory (OCM) · Programmable timers · External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8- or 16-bit SRAM and external peripherals - Up to five devices · DMA support for memory and UARTs. - Scatter-gather chaining supported - Four channels · PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Asynchronous PCI Bus interface · Software accessible event counters · Two serial ports (16750 compatible UART) · One IIC interface · General purpose I/O (GPIO) available · Supports JTAG for board level testing · Internal processor local Bus (PLB) runs at SDRAM interface frequency · Supports PowerPC processor boot from PCI memory - Internal or external PCI Bus Arbiter · Two Ethernet 10/100Mbps (full-duplex) ports with media independent interface (MII) · Programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive interrupts
Description
Designed specifically to address embedded applications, the PowerPC 405EP (PPC405EP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: IBM CMOS SA-27E, 0.18 µm (0.11 µm Leff) Package: 31mm, 385-ball, enhanced plastic ball grid array (E-PBGA) Power (typical): 1.2W at 200MHz
3/19/03
While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Contents
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O Specifications--Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O Specifications--Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Figures
PPC405EP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 31 mm, 385-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Ordering, PVR, and JTAG Information
This section provides the part number nomenclature. For availability, contact your local IBM sales office.
Product Name PPC405EP PPC405EP PPC405EP PPC405EP PPC405EP PPC405EP Order Part Number1 IBM25PPC405EP-3GB133C IBM25PPC405EP-3GB133CZ IBM25PPC405EP-3GB200C IBM25PPC405EP-3GB200CZ IBM25PPC405EP-3GB266C IBM25PPC405EP-3GB266CZ Processor Frequency 133 MH z 133 MH z 200 MH z 200 MH z 266 MH z 266 MH z Package 31 mm, 385 E-PBGA 31 mm, 385 E-PBGA 31 mm, 385 E-PBGA 31 mm, 385 E-PBGA 31 mm, 385 E-PBGA 31 mm, 385 E-PBGA Rev Level B B B B B B PVR Value 0x51210950 0x51210950 0x51210950 0x51210950 0x51210950 0x51210950 JTAG ID 0 x2 0 2 6 7 0 4 9 0 x2 0 2 6 7 0 4 9 0 x2 0 2 6 7 0 4 9 0 x2 0 2 6 7 0 4 9 0 x2 0 2 6 7 0 4 9 0 x2 0 2 6 7 0 4 9
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PowerPC 405EP Embedded Processor User's Manual for details on accessing these registers. Order Part Number Key
IBM25PPC405EP-3GB266Cx
Shipping Package Blank = Tray Z = Tape and reel IBM Part Number Operational Case Temperature Range (-40 °C to +85 °C) Processor Speed 266 = 266MHz 200 = 200MHz 133 = 133MHz Revision Level
Grade 3 Reliability
Package 31mm, 385 E-PBGA
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Preliminary
PowerPC 405EP Embedded Processor Data Sheet
PPC405EP Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control R es et Timers MMU Po wer M gm t DOCM IOCM OC M SRAM
Ev ent Count ers
OC M Control
DCR s UART x2
PPC405 Processor Core JTAG 1 6K B D-Cache DCU Trace ICU
DCR Bus
GPIO
IIC
GPT
16KB I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA Controller (4-Channel)
OPB Bridge
M AL
Ethernet x2
Ar b
Processor Local Bus (PLB)
SDRAM Controller
External Bu s Controller 29-bit addr 16-bit data
PCI Bridge
13-bit addr 32-bit data
66 MHz max (async)
MII
The PPC405EP is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
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