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Part: 405GP
Category:
Microprocessors
-> RISC
-> PowerPC Family
Description: Embedded Controller
Company: IBM Corporation
Datasheet: Download 405GP datasheet File size : 156 kB
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Datasheet text preview:
PowerPC 405GP Embedded Processor Data Sheet
Features
· IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz · PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications · 4 KB on-chip memory (OCM) · External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported · DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels · PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Synchronous or asynchronous PCI Bus interface - Internal or external PCI Bus Arbiter · Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII) · Programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive interrupts · Programmable timers · Two serial ports (16550 compatible UART) · One IIC interface · General purpose I/O (GPIO) available · Supports JTAG for board level testing · Internal processor local Bus (PLB) runs at SDRAM interface frequency · Supports PowerPC processor boot from PCI memory
Description
Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: IBM CMOS SA-12E, 0.25 µm (0.18 µm Leff) Package: 456-ball (35mm or 27mm), or 413-ball (25mm) enhanced plastic ball grid array (E-PBGA) Power (typical): 1.5W at 200MHz, 2W at 266MHz
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PowerPC 405GP Embedded Processor Data Sheet
Contents
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Signals Listed by Ball Assignment--413-Ball Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Signals Listed by Ball Assignment--456-Ball Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O Specifications--All speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O Specifications--200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I/O Specifications--266MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PPC405GP Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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PowerPC 405GP Embedded Processor Data Sheet
Figures
PPC405GP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 25 mm, 413-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 27 mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 35 mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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PowerPC 405GP Embedded Processor Data Sheet
Ordering, PVR, and JTAG Information
Processor Frequency 200 MH z 200 MH z 200 MH z 200 MH z 200 MH z 200 MH z 266 MH z 266 MH z 266 MH z 266 MH z 266 MH z 266 MH z Rev Level E E E E E E E E E E E E
Product Name PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP
Order Part Number1 IBM25PPC405GP-3BE200C IBM25PPC405GP3BE200CZ IBM25PPC405GP-3DE200C IBM25PPC405GP-3DE200CZ IBM25PPC405GP-3EE200C IBM25PPC405GP-3EE200CZ IBM25PPC405GP-3BE266C IBM25PPC405GP-3BE266CZ IBM25PPC405GP-3DE266C IBM25PPC405GP-3DE266CZ IBM25PPC405GP-3EE266C IBM25PPC405GP-3EE266CZ
Package 35 mm, 456 E-PBGA 35 mm, 456 E-PBGA 27 mm, 456 E-PBGA 27 mm, 456 E-PBGA 25 mm, 413 E-PBGA 25 mm, 413 E-PBGA 35 mm, 456 E-PBGA 35 mm, 456 E-PBGA 27 mm, 456 E-PBGA 27 mm, 456 E-PBGA 25 mm, 413 E-PBGA 25 mm, 413 E-PBGA
PVR Value 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145
JTAG ID 0 x4 2 0 5 0 0 4 9 0 x4 2 0 5 0 0 4 9 0x42050049 0x42050049 0 x4 2 0 5 0 0 4 9 0x42050049 0 x4 2 0 5 0 0 4 9 0x42050049 0x42050049 0x42050049 0 x4 2 0 5 0 0 4 9 0x42050049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
This section provides the part number nomenclature. For availability, contact your local IBM sales office. The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the PowerPC 405GP Embedded Processor User's Manual for details on the register content. Order Part Number Key
IBM25PPC405GP-3BE200Cx
Shipping Package Blank = Tray Z = Tape and reel IBM Part Number Operational Case Temperature Range (-40 °C to +85 °C) Processor Speed 200 M H z 266 M H z Revision Level
Grade 3 Reliability
Package B: 35mm, 456 E-PBGA D: 27mm, 456 E-PBGA E: 25mm, 413 E-PBGA
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PowerPC 405GP Embedded Processor Data Sheet
PPC405GP Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control R es et Timers MMU Po wer M gm t DOCM IOCM OC M SRAM DCRs OC M Control GPIO IIC UART UART
PPC405 Processor Core JTAG 8 KB D-Cache DCU Trace ICU
DCR Bus
16KB I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA Controller (4-Channel)
OPB Bridge
M AL
E t her ne t
Ar b C ode Decompression (CodePack) External Bu s Controller
Processor Local Bus (PLB)
SDRAM Controller
External Bus Master Controller
PCI Bridge
13-bit addr 32-bit data
32-bit addr 32-bit data
66 MHz max (async) 33 MHz max (sync)
MII
The PPC405GP is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
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Others parts begin by 40
40-1 40-2 40-3
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