|
Details, datasheet, quote on part number:405LP
| |
Datasheet text preview:
TM
PowerPC 405LP Embedded Processor
Highly integrated device offering high-performance at ultra-low power
PowerPC 405D4 Embedded Core Highlights Offers high performance, ultra-low power, and a rich peripheral mix for a wide variety of power sensitive embedded applications, including mobile phones, PDAs, game devices, and handheld computers. Application code compatible with all other PowerPC processors. Scalable architecture provides ultra-low power by allowing system software to dynamically adjust frequency and voltage between highest performance and lowest power consumption. Extensive clock gating minimizes active power by disabling clocks to registers or entire functional blocks that are currently unused. Achieves ultra-low standby power by storing the processor state in non-volatile memory and removing power from the processor logic. Implements data encryption and voice recognition accelerators to offload CPU and reduce overall active power. Utilizes 64-bit CoreConnectTM bus architecture at up to 133MHz, providing high-speed on-chip performance with low latencies. Provides a platform for developing custom scalable ultra-low power devices · Dynamically scalable 152 MHz to 380 MHz CPU core · Memory Management Unit · 16KB instruction and 16KB data caches · Multiply-Accumulate (MAC) function, including fast multiply unit · 5-stage pipeline · Timers · JTAG and non-invasive trace debug logic SDRAM Controller · 4 chip selects, 4MB to 256MB per bank · PC 133 (133 MHz) compliant · Supports dual- and quad-bank SDRAMs with 11x8 to 13x11 addressing · Programmable address mapping and timing · Separate 32-byte read and 128-byte write buffers · Power management (self-refresh) · 32-bit external data bus width DMA Controller · 4 independent channels · Supports buffered memory-to-peripheral, buffered peripheral-to-memory, and memory-to-memory transfers · Scather/gather capability with command/ data chaining · Internal 32-byte data buffer · Supports memory mapped peripherals Speech Label Accelerator (SLA) · Supports IBM speech label algorithm for speech recognition Multimode External Peripheral Controller · Supports up to 8 banks of ROM, EPROM, SRAM, Flash, and Slave peripheral I/O devices · Up to 66MHz operation · Burst and non-burst devices · 8- and 16-bit byte-addressable data bus width support · Latch data on ready, synchronous or asynchronous · Programmable access timing per device · Programmable address mapping · Single-slot, 8- or 16-bit PCMCIA or CompactFlash (CF+) card LCD Controller · Supports Mono-STN, Color-STN, and TFT panel types · Up to 16 bits per pixel color resolution · 1/4 VGA to XGA (max 2k x 2k) screen size · 64 x 64 pixel hardware graphics cursor Standby Power Management · Supports 3 standby power modes
© International Business Machines Corporation 2001, 2002
PowerPC 405LP Specifications
All Rights Reserved
Technology Performance (est.) Frequency (CPU /SDRAM /EBC) Number of transistors (est.) Typical Core+Caches Power Dissipation (est.) Signal I/Os Power Supply Packaging
0.18 µm (0.13 µm Leff) CMOS SA-27E Copper technology 404 Dhrystone 2.1 MIPS @ 266MHz 202 Dhrystone 2.1 MIPS @ 133MHz 266/133/66 MHz 133/66/33 MHz 5.8 million 500mW @ 380 MHz, 1.8V 53mW @ 152 MHz, 1.0V 22 2 1.0 - 1.8V (logic), 3.3V (I/O) 316-ball, Enhanced PBGA (27mm x 27mm)
Printed in the United States of America 1/20/2003 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM IBM Logo CoreConnect Other company, product and service names may be trademarks or service marks of others. This document contains information on a new product under development by IBM. IBM reserves the right to change or discontinue this product without notice. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM 's product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration.The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS " BASIS WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg.504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at ibm.com. The IBM Microelectronics Division home page can be found at www.chips.ibm.com. PowerPC PowerPC Logo
PowerPC Embedded Tools
· Cryo mode saves processor state to IIC EEPROM and removes power from processor logic · "Instant On" achieved by restoring saved processor state within 200 mS DES Encryption · FIPS PUB 46-3 Data Encryption Standard · DES and Triple-DES variants supported · CBC and ECB encryption modes
CodePack Decompression · Instructions stored in memory in compressed format · Improves code density up to 40% · No loss in instruction set capability Other On-Chip Peripherals · Synchronous serial interface to ADC/ DAC audio codecs · Touch panel controller · 2 serial ports (16550), 8-pin and 4-pin · Master and slave IIC controller, compliant with Phillips I2C spec · Up to 32 general purpose I/Os · Interrupt controller including up to 7 external interrupts
PCMCIA/CFII
On-chip Peripheral Bus (OPB)
SDRAM Controller IBM CodePack Arbiter
Peripheral Controller
Speech Accelerator
LCD Controller DMA Controller
IIC
UART
Processor Local Bus (PLB)
64-Bit
UART
16K I-Cache PLL CPM RTC Voltage Isolated Logic JTAG APU
16K D-Cache MMU
OPB Bridge
GPIO
DES Controller 32-Bit Interrupt Controller
CODEC
405 CPU
TPC
Trace
Timers
Arbiter
PowerPC 405D4 Core
*07SA142
SA14-2610-03
|
|
