|Category||Microprocessors => PowerPC 4xx family|
|Title||PowerPC 4xx family|
|Datasheet||Download 440GP datasheet
PowerPC 440 processor core operating to 500MHz with 32KB I- and D-caches On-chip 8 KB SRAM Selectable processor:bus clock ratios of Double Data Rate (DDR) Synchronous DRAM (SDRAM) 32/64-bit interface operating to 133MHz External Peripheral Bus for up to eight devices with external mastering DMA support for external peripherals, internal UART and memory PCI-X V1.0a interface or 64 bits, to 133MHz) with support for conventional PCI V2.2 Programmable Interrupt Controller supports interrupts from a variety of sources. Programmable General Purpose Timers (GPT) Two serial ports (16750 compatible UART) Two IIC interfaces General Purpose I/O (GPIO) interface available JTAG interface for board level testing Internal Processor Local Bus (PLB) runs at DDR SDRAM interface frequency PowerPC processor boot from PCI memory Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII.Description
Designed specifically to address high-end embedded applications, the PowerPC 440GP (PPC440GP) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. This chip contains a high-performance RISC processor core, DDR SDRAM controller,8KB SRAM, PCI-X bus interface, Ethernet interfaces, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: IBM CMOS µm (0.11 Leff), 5-layer metal Package: 25mm, 552-ball Ceramic Ball Grid Array (CBGA) Power (estimated): Less than 4.0W. Less than W in sleep mode Supply voltages required: 2.5V, 1.8V
Ordering and PVR Information. 4 Address Maps. 5 PowerPC 440 Processor Core. 8 Internal Buses. 8 PCI-X Interface. 9 DDR SDRAM Memory Controller. 10 On-Chip SRAM. 9 External Peripheral Bus Controller (EBC). 10 Ethernet Controller Interface. 11 DMA Controller. 11 Serial Port. 11 IIC Bus Interface. 11 General Purpose Timers (GPT). 12 General Purpose IO (GPIO) Controller. 12 Universal Interrupt Controller (UIC). 12 JTAG. 13 Signal Lists. 15 Signal Description. 39 Heat Sink Mounting Information. 48 Test Conditions. 50 Spread Spectrum Clocking. 52 DDR SDRAM. 59 Initialization. 61 Strapping. 61 EEPROM. 61
PPC440GP Functional Block Diagram. 25mm, 552-Ball CBGA Package. 14 Heat Sink Attached With Spring Clip. 48 Heat Sink Attached With Adhesive. 48 Timing Waveform. 51 Input Setup and Hold Waveform. 54 Output Delay and Float Timing Waveform. 54 DDR SDRAM Write Cycle Timing. 60 DDR SDRAM Read Cycle Timing. 60
System Memory Address Map. 6 DCR Address Map. 7 Signals Listed Alphabetically. 15 Signals Listed by Ball Assignment. 33 Pin Summary. 39 Signal Functional Description. 40 Absolute Maximum Ratings. 47 Package Thermal Specifications. 47 Recommended DC Operating Conditions. 49 Input Capacitance. 50 DC Power Supply Loads. 50 Clocking Specifications. 51 Peripheral Interface Clock Timings. 53 I/O Specifications--All Speeds. 55 I/O Specifications--400, 466, and 500MHz. 58 Strapping Pin Assignments. 61
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