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Details, datasheet, quote on part number:NP2G
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| Part: | NP2G |
| Category: | Communication => Network => Network Processors |
| Description: | The NP2G is a Programmable Network Processor Optimized For Packet Processing at Speeds up to 2 Gbps. |
| Company: | IBM Corporation |
| Datasheet: | Download NP2G datasheet File size : 8705 kB |
| Request For quote: | Find where to buy NP2G
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Datasheet text preview:
IBM PowerNPTM NP2G Network Processor
Preliminary
February 12, 2003
0.1 Copyright and Disclaimer
Copyright International Business Machines Corporation 2003 All Rights Reserved
US Government Users Restricted Rights - Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
Printed in the United States of America February 2003
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo PowerPC PowerNP
IEEE and IEEE 802 are registered trademarks of IEEE in all cases.
Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. Note: This document contains information on products in the sampling and/or initial production phases of development. This information is subject to change without notice. Verify with your IBM field applications engineer that you have the latest version of this document before finalizing a design.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 2070 Route 52, Bldg. 330 Hopewell Junction, NY 12533-6351
The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.ibm.com/chips
np2_ds_title.fm.01 February 12, 2003
IBM PowerNP NP2G Preliminary Network Processor
Contents
About This Book .. 25
Who Should Read This Manual .. 25 Related Publications .......... 25 Conventions Used in This Manual ............. 25
1. General Information ........ 27
1.1 Features ......... 1.2 Ordering Information ..... 1.3 Overview ........ 1.4 NP2G-Based Systems ........... 1.5 Structure ......... 1.5.1 EPC Structure ...... 1.5.1.1 Coprocessors ........ 1.5.1.2 Enhanced Threads ......... 1.5.1.3 Hardware Accelerators ......... 1.5.2 NP2G Memory ..... 1.6 Data Flow ....... 1.6.1 Basic Data Flow ............ 1.6.2 Data Flow in the EPC ... 27 28 29 29 31 32 33 33 34 34 35 35 36
2. Physical Description ....... 39
2.1 Pin Information .............. 2.1.1 Ingress-to-Egress Wrap (IEW) Pins ..... 2.1.2 Flow Control Interface Pins ......... 2.1.3 ZBT Interface Pins ........ 2.1.4 DDR DRAM Interface Pins .......... 2.1.4.1 D3, D2, and D0 Interface Pins ....... 2.1.4.2 D4_0 and D4_1 Interface Pins ...... 2.1.4.3 D6_x Interface Pins ........ 2.1.4.4 DS1 and DS0 Interface Pins ......... 2.1.5 PMM Interface Pins ...... 2.1.5.1 TBI Bus Pins .......... 2.1.5.2 GMII Bus Pins ....... 2.1.5.3 SMII Bus Pins ........ 2.1.6 PCI Pins ...... 2.1.7 Management Bus Interface Pins .......... 2.1.8 Miscellaneous Pins ....... 2.1.9 PLL Filter Circuit ........... 2.1.10 Thermal I/O Usage ..... 2.1.10.1 Temperature Calculation .... 2.1.10.2 Measurement Calibration ............ 2.2 Clocking Domains ......... 2.3 Mechanical Specifications ...... 2.4 IEEE 1149 (JTAG) Compliance ............ 2.4.1 Statement of JTAG Compliance ........... 2.4.2 JTAG Compliance Mode .............
np2_ds_TOC.fm.0 1 February 12, 2003
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Contents
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