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Details, datasheet, quote on part number:IC41C4100-35J
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Datasheet text preview:
IC41C4100 I C 4 1 LV 4 1 0 0
Document Title
1Mx4 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
0A
History
Initial Draft
Draft Date
September 5,2001
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
1
IC41C4100 I C 4 1 LV 4 1 0 0
1M x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
FEATURES
Extended Data-Out (EDO) Page Mode access cycle TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1024 cycles /16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden · Single power supply: 5V ± 10% (IC41C4100) 3.3V ± 10% (IC41LV4100) · Industrail Temperature Range -40oC to 85oC · · · ·
DESCRIPTION The ICSI IC41C4100 and IC41LV4100 is a 1,048,576 x 4-bit
high-performance CMOS Dynamic Random Access Memories. The IC41C4100 offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 1024 random accesses within a single row with access cycle time as short as 12 ns per 4-bit word. These features make the IC41C4100and IC41LV4100 ideally suited for, digital signal processing, high-performance audio systems, and peripheral applications. The IC41C4100 is packaged in a 20-pin 300mil SOJ and 300mil TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. EDO Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -50 50 14 25 20 90 -60 60 15 30 25 110 Unit ns ns ns ns ns
PIN CONFIGURATION 20 (26) Pin SOJ, TSOP-2
I/O0 I/O1 WE RAS A9 1 2 3 4 5 26 25 24 23 22 GND I/O3 I/O2 CAS OE
PIN DESCRIPTIONS
A0-A9 I/O0-3 WE OE RAS CAS Vcc Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection
A0 A1 A2 A3 VCC
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
GND NC
2
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
IC41C4100 I C 4 1 LV 4 1 0 0
FUNCTIONAL BLOCK DIAGRAM
OE WE CAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC
CAS
WE
OE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O3
MEMORY ARRAY 1,048,576 x 4
ADDRESS BUFFERS A0-A9
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
3
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