|
Details, datasheet, quote on part number:IC41C4105
| |
Datasheet text preview:
IC41C4105 and IC41LV4105
Document Title
1Mx4 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
0A
History
Initial Draft
Draft Date
August 1,2001
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR019-0A 08/01/2001
1
IC41C4105 and IC41LV4105
1M x 4 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
FEATURES
· Fast Page Mode Access Cycle · TTL compatible inputs and outputs · Refresh Interval: -- 1,024 cycles/16 ms · Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden · JEDEC standard pinout · Single power supply: 5V ± 10% or 3.3V ± 10% · Byte Write and Byte Read operation via two CAS
DESCRIPTION
The ICSI 4105 Series is a 1,048,576 x 4-bit high-performance CMOS Dynamic Random Access Memory. The Fast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 12 ns per 4-bit word. These features make the 4105 Series ideally suited for highbandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The 4105 Series is packaged in a 20-pin 300mil SOJ and a 20 pin TSOP-2
PRODUCT SERIES OVERVIEW
Part No.
IC41C4105 IC41LV4105 Refresh 1K 1K Voltage 5V ± 10% 3.3V ± 10%
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC) CAS Access Time (tCAC) Column Address Access Time (tAA) Fast Page Mode Cycle Time (tPC) Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -50 50 14 25 20 90 - 6 0 Unit 60 15 30 25 110 ns ns ns ns ns
PIN CONFIGURATION 20 (26) Pin SOJ, TSOP-2
PIN DESCRIPTIONS
A0-A9 I/O0-3 WE OE RAS CAS Vcc GND Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR019-0A 08/01/2001
IC41C4105 and IC41LV4105
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
Function Standby Read Write: Word (Early Write) Read-Write Hidden Refresh RAS-Only Refresh CBR Refresh
Note: 1. EARLY WRITE only.
Read Write(1)
RAS H L L L LHL LHL L HL
CAS H L L L L L H L
WE X H L HL H L X X
OE X L X LH L X X X
Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X
I/O High-Z DOUT DIN DOUT, DIN DOUT DOUT High-Z High-Z
Integrated Circuit Solution Inc.
DR019-0A 08/01/2001
3
|
|
