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Details, datasheet, quote on part number:IC41LV1664
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Datasheet text preview:
IC41C1664 I C 4 1 LV 1 6 6 4
Document Title
64K x 16 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
0A
History
Initial Draft
Draft Date
November 15,2001
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR033-0A 11/15/2001
1
IC41C1664 I C 4 1 LV 1 6 6 4
64K x 16 (1-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
FEATURES
Extended Data-Out (EDO) Page Mode access cycle TTL compatible inputs and outputs; tristate I/O Refresh Interval: 256 cycles /4 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden · Single power supply: 5V ± 10% (IC41C1664) 3.3V ± 10% (IC41LV1664) · Byte Write and Byte Read operation via two CAS · Industrail Temperature Range -40oC to 85oC · · · ·
performance CMOS Dynamic Random Access Memories. The IC41C1664 offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 256 random accesses within a single row with access cycle time as short as 10 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IC41C1664 ideal for use in 16-, 32-bit wide data bus systems. These features make the IC41C1664 and IC41LV1664 ideally suited for high-bandwidth graphics, digital signal processing, h i g h - p e r f o r m a n c e computing systems, and peripheral applications. The IC41C1664 is packaged in a 40-pin 400mil SOJ and 400mil TSOP-2.
DESCRIPTION The ICSI IC41C1664 and IC41LV1664 is a 65,536 x 16-bit high-
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. EDO Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -25 25 8 12 15 43 -30 30 9 16 20 55 -35 35 10 18 23 65 -40 40 11 20 25 75 Unit ns ns ns ns ns
PIN CONFIGURATIONS
40-Pin TSOP-2
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8
40-Pin SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A7 I/O0-15 WE OE RAS UCAS LCAS Vcc GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Power Ground No Connection
NC NC WE RAS NC A0 A1 A2 A3 VCC
11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 25 24 23 22 21
NC LCAS UCAS OE A8 A7 A6 A5 A4 GND
NC WE RAS NC A0 A1 A2 A3 VCC
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Integrated Circuit Solution Inc.
DR033-0A 11/15/2001
IC41C1664 I C 4 1 LV 1 6 6 4
FUNCTIONAL BLOCK DIAGRAM
OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC OE
CAS
WE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY 65,536 x 16
ADDRESS BUFFERS A0-A7
Integrated Circuit Solution Inc.
DR033-0A 11/15/2001
3
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