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Details, datasheet, quote on part number:IC41LV1665-30K
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Datasheet text preview:
IC41C1665 I C 4 1 LV 1 6 6 5
Document Title
64K x16 bit Dynamic RAM with Fast Page Mode
Revision History
Revision No
0A
History
Initial Draft
Draft Date
October 17,2001
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
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IC41C1665 I C 4 1 LV 1 6 6 5
64K x 16 (1-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
FEATURES
· · · · · ·
DESCRIPTION
· ·
The ICSI IC41C1665 and the IC41LV1665 are 65,536 x 16Fast access and cycle time bit high-performance CMOS Dynamic Random Access TTL compatible inputs and outputs Memory. Fast Page Mode allows 256 random accesses Refresh Interval: 256 cycles/4 ms within a single row with access cycle time as short as 12 ns per 16-bit word. The Byte Write control, of upper and lower Refresh Mode: RAS-Only, CAS-before-RAS byte, makes these devices ideal for use in 16-, 32-bit wide (CBR), Hidden data bus systems. JEDEC standard pinout These features make the IC41C1665 and the IC41LV1665 Single power supply: ideally suited for high band-width graphics, digital signal -- 5V ± 10% (IC41C1665) processing, high-performance computing systems, and peripheral applications. -- 3.3V ± 10% (IC41LV1665) The IC41C1665 and the IC41LV1665 are packaged in a 40Byte Write and Byte Read operation via pin, 400mil SOJ and TSOP-2. two CAS Available in 40-pin SOJ and TSOP-2 KEY TIMING PARAMETERS
Parameter -25 -30 30 9 16 20 55 -35 35 10 18 23 65 -40 40 11 20 25 75 Unit ns ns ns ns ns
Max. RAS Access Time (tRAC) 25 Max. CAS Access Time (tCAC) 8 Max. Column Address Access Time (tAA) 1 2 Min. Fast Page Mode Cycle Time (tPC) 15
PIN CONFIGURATIONS 40-Pin TSOP-2
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8
Min. Read/Write Cycle Time (tRC)
43
40-Pin SOJ
VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A7 I/O0-I/O15 WE OE RAS UCAS LCAS Vcc GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Power Ground No Connection
NC NC WE RAS NC A0 A1 A2 A3 VCC
11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 25 24 23 22 21
NC LCAS UCAS OE NC A7 A6 A5 A4 GND
NC WE RAS NC A0 A1 A2 A3 VCC
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
IC41C1665 I C 4 1 LV 1 6 6 5
FUNCTIONAL BLOCK DIAGRAM
OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC
CAS
WE
OE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY 65,536 x 16
ADDRESS BUFFERS A0-A7
Integrated Circuit Solution Inc.
DR031-0A 10/17/2001
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