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Details, datasheet, quote on part number:IC42S16400-7T
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Datasheet text preview:
IC42S16400
Document Title
1M x 16Bit x 4 Banks (64-MBIT) SDRAM
Revision History
Revision No
0A 0B 0C
History
Initial Draft Revise DC OPERATING CONDITIONS 1. add -6ns speed grade 2. obsolete 8Mx8 configuration 3. obsolete Low power version 4. obsolete -8ns speed grade
Draft Date
Remark
Demcember 20,2001 April 15,2002 Novembver 22,2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR034-0C 11/22/2002
1
IC42S16400
1M x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
· Single 3.3V (± 0.3V) power supply · High speed clock cycle time -6: 166MHz, -7: 133MHz · Fully synchronous operation referenced to clock rising edge · Possible to assert random column access in every cycle · Quad internal banks contorlled by A12 & A13 (Bank Select) · Byte control by LDQM and UDQM for IC42S16400 · Programmable Wrap sequence (Sequential / Interleave) · Programmable burst length (1, 2, 4, 8 and full page) · Programmable CAS latency (2 and 3) · Automatic precharge and controlled precharge · CBR (Auto) refresh and self refresh · LVTTL compatible inputs and outputs · 4,096 refresh cycles / 64ms · Burst termination by Burst stop and Precharge command · Package 400mil 54-pin TSOP-2
DESCRIPTION
The IC42S16400 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 1,048,576 x 16 x 4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up to 166MHz for -6. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOP-2.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc.
DR034-0C 11/22/2002
IC42S16400
PIN CONFIGURATIONS
54-Pin TSOP-2
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
PIN DESCRIPTIONS
CLK CKE CS RAS CAS WE DQ0 ~ DQ15 Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O DQM A0-11 BA0,1 VDD VDDQ V SS VSSQ DQ Mask Enable Address Input Bank Address Power Supply Power Supply for DQ Ground Ground for DQ
Integrated Circuit Solution Inc.
DR034-0C 11/22/2002
3
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