|
Details, datasheet, quote on part number:IC42S32200/L-8B
| |
Datasheet text preview:
IC42S32200 IC42S32200L
Document Title
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Revision History Revision No
0A
History
Initial Draft
Draft Date
September 26,2002
Remark
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR036-0A 09/26/2002
1
IC42S32200 IC42S32200L
512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
· Partial refresh · Concurrent auto precharge · Clock rate:200/166/143/125 MHz · Fully synchronous operation · Internal pipelined architecture · Four internal banks (512K x 32bit x 4bank) · Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write · Burst stop function · Individual byte controlled by DQM0-3 · Auto Refresh and Self Refresh · 4096 refresh cycles/64ms · Single +3.3V ±0.3V power supply · Interface:LVTTL · Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm · Pb-free package is available.
DESCRIPTION
The ICSI IC42S32200 and IC42S32200L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits.Read and write accesses start at a selected locations in a programmed sequence. Accesses begin with the registration of a BankActive command which is then followed by a Read or Write command The ICSI IC42S32200 and IC42S32200L provides for programmable Read or Write burst lengths of 1,2,4,8,or full page, with a burst termination operation. An auto precharge function may be enable to provide a self-timed row precharge that is initiated at the end of the burst sequence.The refresh functions,either Auto or Self Refresh are easy to use. By having a programmable mode register,the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR036-0A 09/26/2002
IC42S32200 IC42S32200L
FUNCTIONAL BLOCK DIAGRAM
Column Decoder
Row Decoder
2048 X 256 X 32 C E L L A R R AY (BANK #0)
Sense
Amplifier
CLK
CLOCK BUFFER
CONTROL SIGNAL G E N E R AT O R
CKE Sense CS# RAS# CAS# WE#
Row Decoder
Amplifier
COMMAND DECODER MODE REGISTER
2048 X 256 X 32 C E L L A R R AY (BANK #1) Col um n Decoder
COLUMN C O U N TE R A10/AP Column Decoder
Row Decoder
A0 A9 BS0 BS1
ADDRESS BUFFER
2048 X 256 X 32 CELL ARRAY (BANK #2)
Sense Amplifier
REFRESH COUNTER
Sense DQ BUFFER DQ0 D Q 31
Decoder
Amplifier
Row
2048 X 256 X 32 CELL ARRAY (BANK #3)
Column
Decoder
DQM0~3
Integrated Circuit Solution Inc.
DR036-0A 09/26/2002
3
|
|
