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Details, datasheet, quote on part number:IC42S8200-7TI
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Datasheet text preview:
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.EATURES
1 M e g x 8 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
DESCRIPTION 1+51's 16Mb Synchronous DRAM IC42S8200 is organized
as a 1Meg x 8-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
Clock frequency: 166, 143, 125, 100 MHz .ully synchronous; all signals referenced to a positive clock edge Two banks can be operated simultaneously and independently Dual internal bank controlled by A11 (bank select) Single 3.3V power supply LVTTL interface Programmable burst length (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto refresh, self refresh 4096 refresh cycles every 128 ms Random column address every clock cycle Programmable +)5 latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Package 400mil 44-pin TSOP-2
PIN CON.IGURATIONS
44-Pin TSOP-2
VCC I/O0 GNDQ I/O1 VccQ I/O2 GNDQ I/O3 VccQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
GND I/O7 GNDQ I/O6 VCCQ I/O5 GNDQ I/O4 VCCQ NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A11 A0-A10 A11 A0-A8 I/O0 to I/O7 CLK CKE CS RAS Address Input Row Address Input Bank Select Address Column Address Input Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command CAS WE DQM Vcc GND VccQ GNDQ NC Column Address Strobe Command Write Enable Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR018-0A 07/10/2001
1
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PIN .UNCTIONS
P i n No. 17 to 21 24 to 29 Symbol A0-A10 Type Input Pin . u n c t i o n (In Detail) A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input and A0-A7 as column address inputs during read or write command input. A10 is also used to determine the precharge mode during other commands. If A10 is LOW during precharge command, the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged. When A10 is HIGH in read or write command cycle, the precharge starts automatically after the burst access. These signals become part of the OP CODE during mode register set command input. A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is selected. This signal becomes part of the OP CODE during mode register set command input. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. The CKE input determines whether the CLK input is enabled within the device. When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid. When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. I/O0 to I/O7 are I/O pins. In read mode,DQM controls the output buffer. When DQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when DQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, DQM control the input buffer. When DQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When DQM is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VCCQ is the output buffer power supply. VCC is the device internal power supply. GNDQ is the output buffer ground. GND is the device internal ground.
16
A11
Input Pin
13 31
CAS CKE
Input Pin Input Pin
32 15 2,4,6,8 37,39,41,43 33
CLK CS I/O0 to I/O7 DQM,
Input Pin Input Pin I/O Pin Input Pin
14 12 5,9,36,40 1,22 3,7,38,42 23,44
RAS WE VCCQ VCC GNDQ GND
Input Pin Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin
2
Integrated Circuit Solution Inc.
DR018-0A 07/10/2001
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.UNCTIONAL BLOCK DIAGRAM
COMMAND DECODER & CLOCK GENERATOR
ROW DECODER
CLK CKE CS RAS CAS WE A11
MODE REGISTER
11
11
ROW ADDRESS BUFFER
MEMORY CELL ARRAY
2048
11
BANK 0
DQM
SENSE AMP I/O GATE
A10
9
COLUMN ADDRESS BUFFER
BURST COUNTER
COLUMN ADDRESS LATCH
DATA IN BUFFER
8 8
512
COLUMN DECODER
ROW DECODER
MULTIPLEXER
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
REFRESH CONTROLLER
SELF REFRESH CONTROLLER
I/O 0-7
9
512
SENSE AMP I/O GATE
REFRESH COUNTER
DATA OUT BUFFER
8 8
11
ROW ADDRESS LATCH
11
ROW ADDRESS BUFFER
2048
MEMORY CELL ARRAY
Vcc/VccQ GND/GNDQ
BANK 1
11
S16BLK.eps
Integrated Circuit Solution Inc.
DR018-0A 07/10/2001
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