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Details, datasheet, quote on part number:IC61LV256-8T
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Datasheet text preview:
IC61LV256
Document Title
32K x 8 Hight Speed SRAM with 3.3V
Revision History
Revision No
0A
History
Initial Draft
Draft Date
April 19,2002
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
AHSR027-0A 04/19/2002
1
IC61LV256
32K x 8 HIGH SPEED CMOS STATIC RAM
FEATURES
· High-speed access times: -- 8, 10, 12, 15 ns · Automatic power-down when chip is deselected · CMOS low power operation -- 345 mW (max.) operating -- 7 mW (max.) CMOS standby · TTL compatible interface levels · Single 3.3V power supply · Fully static operation: no clock or refresh required · Three-state outputs
DESCRIPTION T h e ICSI IC61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ICSI's
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum. When CE is HIGH (deselected), the device assumes a standby m o d e at which the power dissipation is reduced to 600 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC61LV256 is available in the JEDEC standard 28-pin, 300mil SOJ and the 8*13.4mm TSOP-1 package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
256 X 1024 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE OE WE CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc.
AHSR027-0A 04/19/2002
IC61LV256
PIN CONFIGURATION
28-Pin SOJ
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
22 23 24 25 26 27 28 1 2 3 4 5 6 7
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
PIN DESCRIPTIONS
A0-A14 CE OE WE I/O0-I/O7 Vcc GND Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output Power Ground
TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM TBIAS TSTG PD IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value 0.5 to +4.6 0.5 to +4.6 10 to +85 45 to +90 65 to +150 1 ±20 Unit V V °C °C W mA
Com. Ind.
Notes: 1 . Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc.
AHSR027-0A 04/19/2002
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