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Details, datasheet, quote on part number:IC62LV1024ALL-70BI
 
 
Part:IC62LV1024ALL-70BI
Category:Memory => SRAM => Async. SRAM
Description:
Company:Integrated Circuit Solution
Datasheet:Download IC62LV1024ALL-70BI datasheet   File size : 130 kB
Request For quote:  Find where to buy IC62LV1024ALL-70BI
 



Datasheet text preview:
I C 6 2 LV 1 0 2 4 A L I C 6 2 LV 1 0 2 4 A L L
Document Title
128K x 8 Ultra Low Power and Low VCC SRAM
Revision History
Revision No
0A
History
Initial Draft
Draft Date
Remark
September 13,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
1
I C 6 2 LV 1 0 2 4 A L I C 6 2 LV 1 0 2 4 A L L
128K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM
FEATURES
· Access times of 45, 55, and 70 ns · Low active power: 60 mW (typical) · Low standby power: 15 µW (typical) CMOS standby · Low data retention voltage: 2V (min.) · Available in Low Power (-L) and Ultra Low Power (-LL) · Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications · TTL compatible inputs and outputs · Single 2.7V to 3.3V power supply
DESCRIPTION The ICSI IC62LV1024AL and IC62LV1024ALL are low power
and low Vcc,131,072-word by 8-bit CMOS static RAMs. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62LV1024AL and IC62LV1024ALL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1, 450mil SOP and 48-pin 6*8mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
512 X 2048 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1 CE2 OE WE CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
I C 6 2 LV 1 0 2 4 A L I C 6 2 LV 1 0 2 4 A L L
PIN CONFIGURATION
32-Pin SOP
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
PIN CONFIGURATION
32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
48-Pin 6x8mm TF-BGA
PIN DESCRIPTIONS
A0-A16 Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground CE1 CE2 OE WE I/O0-I/O7 NC Vcc GND
1 A B C D E F G H
A0 I/O5 I/O6 GND Vcc I/O7 I/O8 A9
2
A1 A2
3
CE2 WE NC
4
A3 A4 A5
5
A6 A7
6
A8 I/O1 I/O2 Vcc GND
NC OE A10 CE1 A11
NC A16 A12 A15 A13
I/O3 I/O4 A14
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0°C to +70°C ­40°C to +85°C VCC 2.7V to 3.3V 2.7V to 3.3V
Integrated Circuit Solution Inc.
LPSR017-0A 09/13/2001
3