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Details, datasheet, quote on part number:IC62LV12816DL-100B
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Datasheet text preview:
IC62LV12816DL IC62LV12816DLL
Document Title
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
0A
History
Initial Draft
Draft Date
June 7,2002
Remark
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
1
IC62LV12816DL IC62LV12816DLL
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
FEATURES
· High-speed access times: 55, 70, 100 ns · CMOS low power operation --60mW (typical)* operating --3µW (typical)* CMOS standby · TTL compatible interface levels · Single 2.7V-3.6V Vcc power supply · Fully static operation: no clock or refresh required · Three state outputs · Data control for upper and lower bytes · Industrial temperature available · Available in the 44-pin TSOP-2 and 48-pin 6x8mm TF-BGA · CE2 pin only for 48-pin TF-BGA.
* Typical values are measured at VCC=3.0V, TA=25°C
Preliminary
DESCRIPTION The ICSI IC62LV12816DL and IC62LV12816DLL are lowpower,2,097,152 bit static RAMs organized as 131,072 words by 16 bits. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE1 is HIGH or when CE2 is low (deselected) or both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE1, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC62LV12816DL and IC62LV12816DLL are packaged in the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TFBGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16 MEMORY ARRAY
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE1, CE2 OE WE UB LB CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
IC62LV12816DL IC62LV12816DLL
PIN CONFIGURATIONS
44-Pin TSOP-2
A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
48-Pin TF-BGA (TOP View)
1 A B C D E F G H
LB I/O8 I/O9 GND Vcc I/O14 I/O15 NC
2
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
3
A0 A3 A5 NC NC A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11
6
CE2 I/O0 I/O2 Vcc GND I/O6 I/O7 NC
PIN DESCRIPTIONS
A0-A16 I/O0-I/O15 CE1 CE2 OE WE Address Inputs Data Input/Output Chip Enable1 Input Chip Enable2 Input, BGA only Output Enable Input Write Enable Input LB UB NC Vcc GND Lower-byte Control (l/O0-I/O7) Upper-byte Control (l/O8-I/O15) No Connection Power Ground
TRUTH TABLE
Mode Not Selected WE CE1 H X L L L L L L L L L CE2 X L H H H H H H H H H OE X X X H H L L L X X X LB X X H L X L H L L H L UB X X H X L H L L H L L I/O0/-I/O7 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O PIN I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current Standby Standby Standby Active Active Active Active Active Active Active Active
X X X Output Disabled H H Read H H H Write L L L
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
3
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