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Part: IS42S8800L-8TI
Category:
Memory
-> DRAM
-> SDR SDRAM
Description:
Company: Integrated Circuit Solution
Datasheet: Download IS42S8800L-8TI datasheet File size : 673 kB
Request For quote: Find where to buy IS42S8800L-8TI
Datasheet text preview:
IS42S8800/IS42S8800L IS42S16400/IS42S16400L
FEATURES
Single 3.3V (± 0.3V) power supply High speed clock cycle time -7: 133MHz, -8: 100MHz Fully synchronous operation referenced to clock rising edge Possible to assert random column access in every cycle Quad internal banks contorlled by A12 & A13 (Bank Select) Byte control by LDQM and UDQM for IS42S16400 Programmable Wrap sequence (Sequential / Interleave) Programmable burst length (1, 2, 4, 8 and full page) Programmable /CAS latency (2 and 3) Automatic precharge and controlled precharge CBR (Auto) refresh and self refresh X8, X16 organization LVTTL compatible inputs and outputs 4,096 refresh cycles / 64ms Burst termination by Burst stop and Precharge command Package 400mil 54-pin TSOP-2
2(1)M Words x 8(16) Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The IS42S8800 and IS42S16400 are high-speed 67, 108,864-bit synchronous dynamic random-access moeories, organized as 2,097,152 x 8 x 4 and 1,048, 576 x 16 x 4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up to 133MHz for -7. All input and outputs are synchronized with the postive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are pack-aged in 54-pin TSOP-2.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR007-0A
1
IS42S8800/IS42S8800L IS42S16400/IS42S16400L
PIN CONFIGURATIONS
54-Pin TSOP-2 (IS42S8800) 54-Pin TSOP-2 (IS42S16400)
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
PIN DESCRIPTIONS
CLK CKE CS RAS CAS WE DQ0 ~ DQ15 Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O DQM A0-11 BA0,1 VDD VDDQ VSS VSSQ DQ Mask Enable Address Input Bank Address Power Supply Power Supply for DQ Ground Ground for DQ
2
Integrated Circuit Solution Inc.
DR007-0A
IS42S8800/IS42S8800L IS42S16400/IS42S16400L
FUNCTIONAL BLOCK DIAGRAM
CLK CKE Clock Generator
Address
Mode Register
Row Decoder
Row Address Buffer & Refresh Counter
Bank D Bank C Bank B
Bank A
Sense Amplifier
Command Decoder
CS RAS CAS WE
Control Logic
Input & Output Buffer
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
Data Control Circuit
DQ
Integrated Circuit Solution Inc.
DR007-0A
3
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